From 96104d6a2db42d48a8a89167cc4b2bd3e3e5834e Mon Sep 17 00:00:00 2001 From: Tad Date: Thu, 11 Jan 2018 15:58:04 -0500 Subject: [PATCH] Overclock mako --- Misc/Strong_AES.txt | 5 + .../0001-Overclock.patch | 272 ++++++++++++++++ .../0002-Overclock.patch | 60 ++++ ...rUnderClock.patch => 0003-Overclock.patch} | 301 ++++-------------- .../0004-Overclock.patch | 109 +++++++ .../0005-Overclock.patch | 25 ++ Scripts/LineageOS-14.1/Overclock.sh | 15 +- 7 files changed, 539 insertions(+), 248 deletions(-) create mode 100644 Patches/LineageOS-14.1/android_kernel_lge_mako/0001-Overclock.patch create mode 100644 Patches/LineageOS-14.1/android_kernel_lge_mako/0002-Overclock.patch rename Patches/LineageOS-14.1/android_kernel_lge_mako/{0001-OverUnderClock.patch => 0003-Overclock.patch} (53%) create mode 100644 Patches/LineageOS-14.1/android_kernel_lge_mako/0004-Overclock.patch create mode 100644 Patches/LineageOS-14.1/android_kernel_lge_mako/0005-Overclock.patch diff --git a/Misc/Strong_AES.txt b/Misc/Strong_AES.txt index 9226046c..ff0d527a 100644 --- a/Misc/Strong_AES.txt +++ b/Misc/Strong_AES.txt @@ -17,12 +17,17 @@ Benchmarks (Androbench) Rand. Write: 3 MBps AES-128/RSA-2048 Encryption AES-192/RSA-4096 Encryption + AES-192/RSA-4096 Encryption + Overclock AES-256/RSA-4096 Encryption Seq. Read: 26 MBps Seq. Write: 18 MBps Rand. Read: 8 MBps Rand. Write: 3 MBps AES-256/RSA-4096 Encryption + Overclock + Seq. Read: 32 MBps + Seq. Write: 18 MBps + Rand. Read: 9 MBps + Rand. Write: 3 MBps clark-1 AES-128/RSA-2048 Encryption Seq. Read: 50 MBps diff --git a/Patches/LineageOS-14.1/android_kernel_lge_mako/0001-Overclock.patch b/Patches/LineageOS-14.1/android_kernel_lge_mako/0001-Overclock.patch new file mode 100644 index 00000000..9fa6d703 --- /dev/null +++ b/Patches/LineageOS-14.1/android_kernel_lge_mako/0001-Overclock.patch @@ -0,0 +1,272 @@ +From 5858badcc16994ea21140b5a905536d365da45b4 Mon Sep 17 00:00:00 2001 +From: anarkia1976 +Date: Sun, 12 Jan 2014 20:26:27 +0100 +Subject: [PATCH] msm: cpu: overclock: added low (162Mhz) and high (1944Mhz) + cpu + +--- + arch/arm/mach-msm/Kconfig | 13 ++++++ + arch/arm/mach-msm/acpuclock-8064.c | 91 +++++++++++++++++++++++++++++++++++++ + arch/arm/mach-msm/acpuclock-krait.c | 8 +++- + arch/arm/mach-msm/msm_dcvs.c | 5 ++ + 4 files changed, 116 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig +index 890c96e3a1f..814ab1a88b4 100644 +--- a/arch/arm/mach-msm/Kconfig ++++ b/arch/arm/mach-msm/Kconfig +@@ -1633,6 +1633,19 @@ config MSM_CPU_FREQ_MIN + + endif # CPU_FREQ_MSM + ++config LOW_CPUCLOCKS ++ bool "Enable ultra low CPU clocks" ++ default n ++ help ++ Ultra low cpu frequencies enabled for CPU and L2 Cache ++ ++config CPU_OVERCLOCK ++ bool "Enable CPU Overclocking option" ++ default n ++ help ++ Krait overclocking up to 1.9 GHz ++ ++ + config MSM_AVS_HW + bool "Enable Adaptive Voltage Scaling (AVS)" + default n +diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c +index 8262946e016..f40edd3d687 100644 +--- a/arch/arm/mach-msm/acpuclock-8064.c ++++ b/arch/arm/mach-msm/acpuclock-8064.c +@@ -47,7 +47,11 @@ static struct scalable scalable[] __initdata = { + .aux_clk_sel = 3, + .sec_clk_sel = 2, + .l2cpmr_iaddr = 0x4501, ++#ifdef CONFIG_CPU_OVERCLOCK ++ .vreg[VREG_CORE] = { "krait0", 1450000 }, ++#else + .vreg[VREG_CORE] = { "krait0", 1300000 }, ++#endif + .vreg[VREG_MEM] = { "krait0_mem", 1150000 }, + .vreg[VREG_DIG] = { "krait0_dig", 1150000 }, + .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 }, +@@ -58,7 +62,11 @@ static struct scalable scalable[] __initdata = { + .aux_clk_sel = 3, + .sec_clk_sel = 2, + .l2cpmr_iaddr = 0x5501, ++#ifdef CONFIG_CPU_OVERCLOCK ++ .vreg[VREG_CORE] = { "krait1", 1450000 }, ++#else + .vreg[VREG_CORE] = { "krait1", 1300000 }, ++#endif + .vreg[VREG_MEM] = { "krait1_mem", 1150000 }, + .vreg[VREG_DIG] = { "krait1_dig", 1150000 }, + .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 }, +@@ -69,7 +77,11 @@ static struct scalable scalable[] __initdata = { + .aux_clk_sel = 3, + .sec_clk_sel = 2, + .l2cpmr_iaddr = 0x6501, ++#ifdef CONFIG_CPU_OVERCLOCK ++ .vreg[VREG_CORE] = { "krait2", 1450000 }, ++#else + .vreg[VREG_CORE] = { "krait2", 1300000 }, ++#endif + .vreg[VREG_MEM] = { "krait2_mem", 1150000 }, + .vreg[VREG_DIG] = { "krait2_dig", 1150000 }, + .vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 }, +@@ -80,7 +92,11 @@ static struct scalable scalable[] __initdata = { + .aux_clk_sel = 3, + .sec_clk_sel = 2, + .l2cpmr_iaddr = 0x7501, ++#ifdef CONFIG_CPU_OVERCLOCK ++ .vreg[VREG_CORE] = { "krait3", 1450000 }, ++#else + .vreg[VREG_CORE] = { "krait3", 1300000 }, ++#endif + .vreg[VREG_MEM] = { "krait3_mem", 1150000 }, + .vreg[VREG_DIG] = { "krait3_dig", 1150000 }, + .vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 }, +@@ -116,6 +132,24 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = { + }; + + static struct l2_level l2_freq_tbl[] __initdata = { ++#ifdef CONFIG_LOW_CPUCLOCKS ++ [0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 }, ++ [1] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 }, ++ [2] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 }, ++ [3] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 }, ++ [4] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 }, ++ [5] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 }, ++ [6] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 }, ++ [7] = { { 702000, HFPLL, 1, 0x1A }, 1150000, 1150000, 4 }, ++ [8] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 }, ++ [9] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 }, ++ [10] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 }, ++ [11] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 }, ++ [12] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 5 }, ++ [13] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 }, ++ [14] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 }, ++ [15] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 }, ++#else + [0] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 }, + [1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 }, + [2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 }, +@@ -131,11 +165,19 @@ static struct l2_level l2_freq_tbl[] __initdata = { + [12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 }, + [13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 }, + [14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 }, ++#endif + { } + }; + + static struct acpu_level tbl_slow[] __initdata = { ++#ifdef CONFIG_LOW_CPUCLOCKS ++ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 }, ++ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 }, ++ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 }, ++ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 925000 }, ++#else + { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 }, ++#endif + { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 }, +@@ -157,11 +199,25 @@ static struct acpu_level tbl_slow[] __initdata = { + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 }, ++#ifdef CONFIG_CPU_OVERCLOCK ++ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 }, ++ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 }, ++ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1400000 }, ++ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1425000 }, ++ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1450000 }, ++#endif + { 0, { 0 } } + }; + + static struct acpu_level tbl_nom[] __initdata = { ++#ifdef CONFIG_LOW_CPUCLOCKS ++ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 }, ++ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 }, ++ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 }, ++ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 875000 }, ++#else + { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 }, ++#endif + { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 }, +@@ -183,11 +239,25 @@ static struct acpu_level tbl_nom[] __initdata = { + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 }, ++#ifdef CONFIG_CPU_OVERCLOCK ++ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 }, ++ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 }, ++ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1350000 }, ++ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1375000 }, ++ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1400000 }, ++#endif + { 0, { 0 } } + }; + + static struct acpu_level tbl_fast[] __initdata = { ++#ifdef CONFIG_LOW_CPUCLOCKS ++ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, ++ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, ++ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 }, ++ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 }, ++#else + { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 }, ++#endif + { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 }, +@@ -209,11 +279,25 @@ static struct acpu_level tbl_fast[] __initdata = { + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 }, ++#ifdef CONFIG_CPU_OVERCLOCK ++ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 }, ++ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 }, ++ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1300000 }, ++ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1325000 }, ++ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1350000 }, ++#endif + { 0, { 0 } } + }; + + static struct acpu_level tbl_faster[] __initdata = { ++#ifdef CONFIG_LOW_CPUCLOCKS ++ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, ++ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, ++ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 }, ++ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 }, ++#else + { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 }, ++#endif + { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 }, +@@ -235,6 +319,13 @@ static struct acpu_level tbl_faster[] __initdata = { + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1125000 }, ++#ifdef CONFIG_CPU_OVERCLOCK ++ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1150000 }, ++ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 }, ++ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 }, ++ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1275000 }, ++ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1300000 }, ++#endif + { 0, { 0 } } + }; + +diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c +index e3a3f5486e4..97f6f3909f5 100644 +--- a/arch/arm/mach-msm/acpuclock-krait.c ++++ b/arch/arm/mach-msm/acpuclock-krait.c +@@ -45,6 +45,12 @@ + #define PRI_SRC_SEL_HFPLL 1 + #define PRI_SRC_SEL_HFPLL_DIV2 2 + ++#ifdef CONFIG_LOW_CPUCLOCKS ++#define FREQ_TABLE_SIZE 39 ++#else ++#define FREQ_TABLE_SIZE 35 ++#endif ++ + static DEFINE_MUTEX(driver_lock); + static DEFINE_SPINLOCK(l2_lock); + +@@ -913,7 +919,7 @@ static void __init bus_init(const struct l2_level *l2_level) + } + + #ifdef CONFIG_CPU_FREQ_MSM +-static struct cpufreq_frequency_table freq_table[NR_CPUS][35]; ++static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE]; + + static void __init cpufreq_table_init(void) + { +diff --git a/arch/arm/mach-msm/msm_dcvs.c b/arch/arm/mach-msm/msm_dcvs.c +index 1a919fcf577..1d5e289b9b8 100644 +--- a/arch/arm/mach-msm/msm_dcvs.c ++++ b/arch/arm/mach-msm/msm_dcvs.c +@@ -146,7 +146,12 @@ static struct dcvs_core core_list[CORES_MAX]; + + static struct kobject *cores_kobj; + ++#ifdef CONFIG_CPU_OVERCLOCK ++#define DCVS_MAX_NUM_FREQS 20 ++#else + #define DCVS_MAX_NUM_FREQS 15 ++#endif ++ + static struct msm_dcvs_freq_entry cpu_freq_tbl[DCVS_MAX_NUM_FREQS]; + static unsigned num_cpu_freqs; + static struct msm_dcvs_platform_data *dcvs_pdata; +-- +2.15.1 + diff --git a/Patches/LineageOS-14.1/android_kernel_lge_mako/0002-Overclock.patch b/Patches/LineageOS-14.1/android_kernel_lge_mako/0002-Overclock.patch new file mode 100644 index 00000000..ce245eb7 --- /dev/null +++ b/Patches/LineageOS-14.1/android_kernel_lge_mako/0002-Overclock.patch @@ -0,0 +1,60 @@ +From e4ec1877adef9b5c222793f77390b607e5f5c900 Mon Sep 17 00:00:00 2001 +From: anarkia1976 +Date: Wed, 5 Feb 2014 07:15:12 +0100 +Subject: [PATCH] msm: cpu: overclock: added ultra low (81Mhz) cpu clock + frequencies + +--- + arch/arm/mach-msm/acpuclock-8064.c | 4 ++++ + arch/arm/mach-msm/acpuclock-krait.c | 2 +- + 2 files changed, 5 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c +index e15d4b4ff4d..7879be1d564 100644 +--- a/arch/arm/mach-msm/acpuclock-8064.c ++++ b/arch/arm/mach-msm/acpuclock-8064.c +@@ -172,6 +172,7 @@ static struct l2_level l2_freq_tbl[] __initdata = { + + static struct acpu_level tbl_slow[] __initdata = { + #ifdef CONFIG_LOW_CPUCLOCKS ++ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, + { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 }, + { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 }, + //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 }, +@@ -212,6 +213,7 @@ static struct acpu_level tbl_slow[] __initdata = { + + static struct acpu_level tbl_nom[] __initdata = { + #ifdef CONFIG_LOW_CPUCLOCKS ++ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, + { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 }, + { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 }, + //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 }, +@@ -252,6 +254,7 @@ static struct acpu_level tbl_nom[] __initdata = { + + static struct acpu_level tbl_fast[] __initdata = { + #ifdef CONFIG_LOW_CPUCLOCKS ++ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, + { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, + { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, + //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 }, +@@ -292,6 +295,7 @@ static struct acpu_level tbl_fast[] __initdata = { + + static struct acpu_level tbl_faster[] __initdata = { + #ifdef CONFIG_LOW_CPUCLOCKS ++ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, + { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, + { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, + //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 }, +diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c +index 33be3163c63..12db7f9e9f6 100644 +--- a/arch/arm/mach-msm/acpuclock-krait.c ++++ b/arch/arm/mach-msm/acpuclock-krait.c +@@ -46,7 +46,7 @@ + #define PRI_SRC_SEL_HFPLL_DIV2 2 + + #ifdef CONFIG_LOW_CPUCLOCKS +-#define FREQ_TABLE_SIZE 39 ++#define FREQ_TABLE_SIZE 40 + #else + #define FREQ_TABLE_SIZE 35 + #endif diff --git a/Patches/LineageOS-14.1/android_kernel_lge_mako/0001-OverUnderClock.patch b/Patches/LineageOS-14.1/android_kernel_lge_mako/0003-Overclock.patch similarity index 53% rename from Patches/LineageOS-14.1/android_kernel_lge_mako/0001-OverUnderClock.patch rename to Patches/LineageOS-14.1/android_kernel_lge_mako/0003-Overclock.patch index 00b932dc..5c149e46 100644 --- a/Patches/LineageOS-14.1/android_kernel_lge_mako/0001-OverUnderClock.patch +++ b/Patches/LineageOS-14.1/android_kernel_lge_mako/0003-Overclock.patch @@ -1,106 +1,24 @@ -From 96b13d96a52a122a3028cd85b77937688672aebf Mon Sep 17 00:00:00 2001 +From 946a09f5411890b1b1ec945b8c882bfa042f4523 Mon Sep 17 00:00:00 2001 From: anarkia1976 -Date: Tue, 17 Jan 2017 18:26:50 -0500 -Subject: [PATCH] OverUnderClock +Date: Wed, 5 Feb 2014 07:12:48 +0100 +Subject: [PATCH] msm: cpu: overclock: use higher bus speed at lower CPU freqs -Change-Id: I341ea6c07898001ecea1dee2f81f4a05e0058292 +Thanks to @bedalus and @mrg666 + +Bedalus suggested that if lower CPU frequencies can offer higher bus +speed, +GPU use during games wouldn't require higher CPU frequency. +My testing demonstrated 4C drop in CPU temp during 3DMark benchmark. +Still needs to be tested for everyday use. --- - arch/arm/configs/lineageos_mako_defconfig | 2 + - arch/arm/mach-msm/Kconfig | 12 ++ - arch/arm/mach-msm/acpuclock-8064.c | 259 +++++++++++++++++++++--------- - arch/arm/mach-msm/acpuclock-krait.c | 8 +- - arch/arm/mach-msm/msm_dcvs.c | 5 + - 5 files changed, 205 insertions(+), 81 deletions(-) + arch/arm/mach-msm/acpuclock-8064.c | 172 +++++++++++++++++++------------------ + 1 file changed, 88 insertions(+), 84 deletions(-) -diff --git a/arch/arm/configs/lineageos_mako_defconfig b/arch/arm/configs/lineageos_mako_defconfig -index 75d20f2..432caa2 100644 ---- a/arch/arm/configs/lineageos_mako_defconfig -+++ b/arch/arm/configs/lineageos_mako_defconfig -@@ -451,6 +451,8 @@ CONFIG_MSM_IPC_ROUTER_SMD_XPRT=y - # CONFIG_MSM_IPC_ROUTER_SECURITY is not set - # CONFIG_MSM_DALRPC is not set - # CONFIG_MSM_CPU_FREQ_SET_MIN_MAX is not set -+CONFIG_LOW_CPUCLOCKS=y -+CONFIG_CPU_OVERCLOCK=y - CONFIG_MSM_AVS_HW=y - # CONFIG_MSM_HW3D is not set - CONFIG_AMSS_7X25_VERSION_2009=y -diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig -index 5f37d1d..b5ab505 100644 ---- a/arch/arm/mach-msm/Kconfig -+++ b/arch/arm/mach-msm/Kconfig -@@ -1634,6 +1634,18 @@ config MSM_CPU_FREQ_MIN - - endif # CPU_FREQ_MSM - -+config LOW_CPUCLOCKS -+ bool "Enable ultra low CPU clocks" -+ default n -+ help -+ Ultra low cpu frequencies enabled for CPU and L2 Cache -+ -+config CPU_OVERCLOCK -+ bool "Enable CPU Overclocking option" -+ default n -+ help -+ Krait overclocking up to 1.9 GHz -+ - config MSM_AVS_HW - bool "Enable Adaptive Voltage Scaling (AVS)" - default n diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c -index 8262946..611776e 100644 +index 7879be1d564..cd045cf0c97 100644 --- a/arch/arm/mach-msm/acpuclock-8064.c +++ b/arch/arm/mach-msm/acpuclock-8064.c -@@ -47,7 +47,11 @@ static struct scalable scalable[] __initdata = { - .aux_clk_sel = 3, - .sec_clk_sel = 2, - .l2cpmr_iaddr = 0x4501, -+#ifdef CONFIG_CPU_OVERCLOCK -+ .vreg[VREG_CORE] = { "krait0", 1450000 }, -+#else - .vreg[VREG_CORE] = { "krait0", 1300000 }, -+#endif - .vreg[VREG_MEM] = { "krait0_mem", 1150000 }, - .vreg[VREG_DIG] = { "krait0_dig", 1150000 }, - .vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 }, -@@ -58,7 +62,11 @@ static struct scalable scalable[] __initdata = { - .aux_clk_sel = 3, - .sec_clk_sel = 2, - .l2cpmr_iaddr = 0x5501, -+#ifdef CONFIG_CPU_OVERCLOCK -+ .vreg[VREG_CORE] = { "krait1", 1450000 }, -+#else - .vreg[VREG_CORE] = { "krait1", 1300000 }, -+#endif - .vreg[VREG_MEM] = { "krait1_mem", 1150000 }, - .vreg[VREG_DIG] = { "krait1_dig", 1150000 }, - .vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 }, -@@ -69,7 +77,11 @@ static struct scalable scalable[] __initdata = { - .aux_clk_sel = 3, - .sec_clk_sel = 2, - .l2cpmr_iaddr = 0x6501, -+#ifdef CONFIG_CPU_OVERCLOCK -+ .vreg[VREG_CORE] = { "krait2", 1450000 }, -+#else - .vreg[VREG_CORE] = { "krait2", 1300000 }, -+#endif - .vreg[VREG_MEM] = { "krait2_mem", 1150000 }, - .vreg[VREG_DIG] = { "krait2_dig", 1150000 }, - .vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 }, -@@ -80,7 +92,11 @@ static struct scalable scalable[] __initdata = { - .aux_clk_sel = 3, - .sec_clk_sel = 2, - .l2cpmr_iaddr = 0x7501, -+#ifdef CONFIG_CPU_OVERCLOCK -+ .vreg[VREG_CORE] = { "krait3", 1450000 }, -+#else - .vreg[VREG_CORE] = { "krait3", 1300000 }, -+#endif - .vreg[VREG_MEM] = { "krait3_mem", 1150000 }, - .vreg[VREG_DIG] = { "krait3_dig", 1150000 }, - .vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 }, -@@ -115,7 +131,33 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = { +@@ -132,6 +132,14 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = { .name = "acpuclk-8064", }; @@ -113,43 +31,17 @@ index 8262946..611776e 100644 +#endif + static struct l2_level l2_freq_tbl[] __initdata = { -+#ifdef CONFIG_LOW_CPUCLOCKS -+ [0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 }, -+ [1] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 }, -+ [2] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 }, -+ [3] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 }, -+ [4] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 }, -+ [5] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 }, -+ [6] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 }, -+ [7] = { { 702000, HFPLL, 1, 0x1A }, 1150000, 1150000, 4 }, -+ [8] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 }, -+ [9] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 }, -+ [10] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 }, -+ [11] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 }, -+ [12] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 5 }, -+ [13] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 }, -+ [14] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 }, -+ [15] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 }, -+#else - [0] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 }, - [1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 }, - [2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 }, -@@ -131,110 +173,167 @@ static struct l2_level l2_freq_tbl[] __initdata = { - [12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 }, - [13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 }, - [14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 }, -+#endif - { } - }; - - static struct acpu_level tbl_slow[] __initdata = { -+#ifdef CONFIG_LOW_CPUCLOCKS -+ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, -+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 }, -+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 }, -+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 925000 }, -+#else + #ifdef CONFIG_LOW_CPUCLOCKS + [0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 }, +@@ -175,32 +183,31 @@ static struct acpu_level tbl_slow[] __initdata = { + { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, + { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 }, + { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 }, +- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 }, + { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 925000 }, + #else { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 }, + #endif - { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 }, - { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 }, - { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 }, @@ -171,7 +63,6 @@ index 8262946..611776e 100644 - { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 }, - { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 }, - { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 }, -+#endif + { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 975000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 975000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 1000000 }, @@ -193,24 +84,18 @@ index 8262946..611776e 100644 + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1237500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1237500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1250000 }, -+#ifdef CONFIG_CPU_OVERCLOCK -+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 }, -+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 }, -+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1400000 }, -+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1425000 }, -+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1450000 }, -+#endif - { 0, { 0 } } - }; - - static struct acpu_level tbl_nom[] __initdata = { -+#ifdef CONFIG_LOW_CPUCLOCKS -+ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, -+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 }, -+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 }, -+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 875000 }, -+#else + #ifdef CONFIG_CPU_OVERCLOCK + { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 }, + { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 }, +@@ -216,32 +223,31 @@ static struct acpu_level tbl_nom[] __initdata = { + { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, + { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 }, + { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 }, +- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 }, + { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 875000 }, + #else { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 }, + #endif - { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 }, - { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 }, - { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 }, @@ -232,7 +117,6 @@ index 8262946..611776e 100644 - { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 }, - { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 }, - { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 }, -+#endif + { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 925000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 925000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 950000 }, @@ -254,24 +138,18 @@ index 8262946..611776e 100644 + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1187500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1187500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1200000 }, -+#ifdef CONFIG_CPU_OVERCLOCK -+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 }, -+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 }, -+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1350000 }, -+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1375000 }, -+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1400000 }, -+#endif - { 0, { 0 } } - }; - - static struct acpu_level tbl_fast[] __initdata = { -+#ifdef CONFIG_LOW_CPUCLOCKS -+ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, -+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, -+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, -+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 }, -+#else + #ifdef CONFIG_CPU_OVERCLOCK + { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 }, + { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 }, +@@ -257,32 +263,31 @@ static struct acpu_level tbl_fast[] __initdata = { + { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, + { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, + { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, +- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 }, + { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 }, + #else { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 }, + #endif - { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 }, - { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 }, - { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 }, @@ -293,7 +171,6 @@ index 8262946..611776e 100644 - { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 }, - { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 }, - { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 }, -+#endif + { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 875000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 875000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 900000 }, @@ -315,24 +192,18 @@ index 8262946..611776e 100644 + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1137500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1137500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1150000 }, -+#ifdef CONFIG_CPU_OVERCLOCK -+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 }, -+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 }, -+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1300000 }, -+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1325000 }, -+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1350000 }, -+#endif - { 0, { 0 } } - }; - - static struct acpu_level tbl_faster[] __initdata = { -+#ifdef CONFIG_LOW_CPUCLOCKS -+ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, -+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, -+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, -+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 }, -+#else + #ifdef CONFIG_CPU_OVERCLOCK + { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 }, + { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 }, +@@ -298,28 +303,27 @@ static struct acpu_level tbl_faster[] __initdata = { + { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, + { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, + { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, +- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 }, + { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 }, + #else { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 }, + #endif - { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 }, - { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 }, - { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 }, @@ -350,7 +221,6 @@ index 8262946..611776e 100644 - { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1075000 }, - { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1075000 }, - { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1100000 }, -+#endif + { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 875000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 875000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 900000 }, @@ -371,60 +241,3 @@ index 8262946..611776e 100644 { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1100000 }, { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 }, { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 }, - { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1125000 }, -+#ifdef CONFIG_CPU_OVERCLOCK -+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1150000 }, -+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 }, -+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 }, -+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1275000 }, -+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1300000 }, -+#endif - { 0, { 0 } } - }; - -diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c -index e3a3f54..695b709 100644 ---- a/arch/arm/mach-msm/acpuclock-krait.c -+++ b/arch/arm/mach-msm/acpuclock-krait.c -@@ -45,6 +45,12 @@ - #define PRI_SRC_SEL_HFPLL 1 - #define PRI_SRC_SEL_HFPLL_DIV2 2 - -+#ifdef CONFIG_LOW_CPUCLOCKS -+#define FREQ_TABLE_SIZE 40 -+#else -+#define FREQ_TABLE_SIZE 35 -+#endif -+ - static DEFINE_MUTEX(driver_lock); - static DEFINE_SPINLOCK(l2_lock); - -@@ -913,7 +919,7 @@ static void __init bus_init(const struct l2_level *l2_level) - } - - #ifdef CONFIG_CPU_FREQ_MSM --static struct cpufreq_frequency_table freq_table[NR_CPUS][35]; -+static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE]; - - static void __init cpufreq_table_init(void) - { -diff --git a/arch/arm/mach-msm/msm_dcvs.c b/arch/arm/mach-msm/msm_dcvs.c -index 1a919fc..1d5e289 100644 ---- a/arch/arm/mach-msm/msm_dcvs.c -+++ b/arch/arm/mach-msm/msm_dcvs.c -@@ -146,7 +146,12 @@ static struct dcvs_core core_list[CORES_MAX]; - - static struct kobject *cores_kobj; - -+#ifdef CONFIG_CPU_OVERCLOCK -+#define DCVS_MAX_NUM_FREQS 20 -+#else - #define DCVS_MAX_NUM_FREQS 15 -+#endif -+ - static struct msm_dcvs_freq_entry cpu_freq_tbl[DCVS_MAX_NUM_FREQS]; - static unsigned num_cpu_freqs; - static struct msm_dcvs_platform_data *dcvs_pdata; --- -2.9.3 - diff --git a/Patches/LineageOS-14.1/android_kernel_lge_mako/0004-Overclock.patch b/Patches/LineageOS-14.1/android_kernel_lge_mako/0004-Overclock.patch new file mode 100644 index 00000000..964a52a3 --- /dev/null +++ b/Patches/LineageOS-14.1/android_kernel_lge_mako/0004-Overclock.patch @@ -0,0 +1,109 @@ +From 8d6d2378e62e1b5236eea4f35d4405e0271cf4d5 Mon Sep 17 00:00:00 2001 +From: anarkia1976 +Date: Wed, 30 Apr 2014 15:04:21 +0200 +Subject: [PATCH] msm: cpu: overclock: modded for cpu ultra overclock and + normal + +--- + arch/arm/mach-msm/Kconfig | 7 ++++++- + arch/arm/mach-msm/acpuclock-8064.c | 16 ++++++++++++---- + 2 files changed, 18 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig +index 814ab1a88b4..b79e485f71f 100644 +--- a/arch/arm/mach-msm/Kconfig ++++ b/arch/arm/mach-msm/Kconfig +@@ -1643,8 +1643,13 @@ config CPU_OVERCLOCK + bool "Enable CPU Overclocking option" + default n + help +- Krait overclocking up to 1.9 GHz ++ Krait overclocking up to 1.7 GHz + ++config CPU_OVERCLOCK_ULTRA ++ bool "Enable CPU Overclocking option" ++ default n ++ help ++ Krait overclocking up to 1.9 GHz + + config MSM_AVS_HW + bool "Enable Adaptive Voltage Scaling (AVS)" +diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c +index 611776ed185..03974d36bba 100644 +--- a/arch/arm/mach-msm/acpuclock-8064.c ++++ b/arch/arm/mach-msm/acpuclock-8064.c +@@ -47,7 +47,7 @@ static struct scalable scalable[] __initdata = { + .aux_clk_sel = 3, + .sec_clk_sel = 2, + .l2cpmr_iaddr = 0x4501, +-#ifdef CONFIG_CPU_OVERCLOCK ++#ifdef CONFIG_CPU_OVERCLOCK_ULTRA + .vreg[VREG_CORE] = { "krait0", 1450000 }, + #else + .vreg[VREG_CORE] = { "krait0", 1300000 }, +@@ -62,7 +62,7 @@ static struct scalable scalable[] __initdata = { + .aux_clk_sel = 3, + .sec_clk_sel = 2, + .l2cpmr_iaddr = 0x5501, +-#ifdef CONFIG_CPU_OVERCLOCK ++#ifdef CONFIG_CPU_OVERCLOCK_ULTRA + .vreg[VREG_CORE] = { "krait1", 1450000 }, + #else + .vreg[VREG_CORE] = { "krait1", 1300000 }, +@@ -77,7 +77,7 @@ static struct scalable scalable[] __initdata = { + .aux_clk_sel = 3, + .sec_clk_sel = 2, + .l2cpmr_iaddr = 0x6501, +-#ifdef CONFIG_CPU_OVERCLOCK ++#ifdef CONFIG_CPU_OVERCLOCK_ULTRA + .vreg[VREG_CORE] = { "krait2", 1450000 }, + #else + .vreg[VREG_CORE] = { "krait2", 1300000 }, +@@ -92,7 +92,7 @@ static struct scalable scalable[] __initdata = { + .aux_clk_sel = 3, + .sec_clk_sel = 2, + .l2cpmr_iaddr = 0x7501, +-#ifdef CONFIG_CPU_OVERCLOCK ++#ifdef CONFIG_CPU_OVERCLOCK_ULTRA + .vreg[VREG_CORE] = { "krait3", 1450000 }, + #else + .vreg[VREG_CORE] = { "krait3", 1300000 }, +@@ -210,6 +210,8 @@ static struct acpu_level tbl_slow[] __initdata = { + #ifdef CONFIG_CPU_OVERCLOCK + { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 }, + { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 }, ++#endif ++#ifdef CONFIG_CPU_OVERCLOCK_ULTRA + { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1400000 }, + { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1425000 }, + { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1450000 }, +@@ -250,6 +252,8 @@ static struct acpu_level tbl_nom[] __initdata = { + #ifdef CONFIG_CPU_OVERCLOCK + { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 }, + { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 }, ++#endif ++#ifdef CONFIG_CPU_OVERCLOCK_ULTRA + { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1350000 }, + { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1375000 }, + { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1400000 }, +@@ -290,6 +294,8 @@ static struct acpu_level tbl_fast[] __initdata = { + #ifdef CONFIG_CPU_OVERCLOCK + { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 }, + { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 }, ++#endif ++#ifdef CONFIG_CPU_OVERCLOCK_ULTRA + { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1300000 }, + { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1325000 }, + { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1350000 }, +@@ -330,6 +336,8 @@ static struct acpu_level tbl_faster[] __initdata = { + #ifdef CONFIG_CPU_OVERCLOCK + { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1150000 }, + { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 }, ++#endif ++#ifdef CONFIG_CPU_OVERCLOCK_ULTRA + { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 }, + { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1275000 }, + { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1300000 }, +-- +2.15.1 + diff --git a/Patches/LineageOS-14.1/android_kernel_lge_mako/0005-Overclock.patch b/Patches/LineageOS-14.1/android_kernel_lge_mako/0005-Overclock.patch new file mode 100644 index 00000000..bcbadbe1 --- /dev/null +++ b/Patches/LineageOS-14.1/android_kernel_lge_mako/0005-Overclock.patch @@ -0,0 +1,25 @@ +From 0753d75eadea50214530dd5f3efcfa9169a5bd18 Mon Sep 17 00:00:00 2001 +From: Stratos Karafotis +Date: Sat, 1 Jun 2013 23:59:40 +0300 +Subject: [PATCH] msm: cpufreq: Break out early if target frequency is the same + as the current + +Signed-off-by: Stratos Karafotis +--- + arch/arm/mach-msm/cpufreq.c | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c +index d968075548e..ad56ed54ec7 100644 +--- a/arch/arm/mach-msm/cpufreq.c ++++ b/arch/arm/mach-msm/cpufreq.c +@@ -241,6 +241,9 @@ static int msm_cpufreq_target(struct cpufreq_policy *policy, + goto done; + } + ++ if (table[index].frequency == policy->cur) ++ goto done; ++ + pr_debug("CPU[%d] target %d relation %d (%d-%d) selected %d\n", + policy->cpu, target_freq, relation, + policy->min, policy->max, table[index].frequency); diff --git a/Scripts/LineageOS-14.1/Overclock.sh b/Scripts/LineageOS-14.1/Overclock.sh index 68cae3ee..46906c9b 100644 --- a/Scripts/LineageOS-14.1/Overclock.sh +++ b/Scripts/LineageOS-14.1/Overclock.sh @@ -19,8 +19,8 @@ echo "Applying overclocks..." -enter "kernel/huawei/msm8994" -patch -p1 < $patches"android_kernel_huawei_msm8994/0001-Overclock.patch" +enter "kernel/huawei/angler" +patch -p1 < $patches"android_kernel_huawei_angler/0001-Overclock.patch" enter "kernel/lge/bullhead" patch -p1 < $patches"android_kernel_common_msm8992/0001-Overclock.patch" @@ -40,8 +40,15 @@ patch -p1 < $patches"android_kernel_lge_g3/0004-Overclock.patch" enter "kernel/lge/hammerhead" patch -p1 < $patches"android_kernel_lge_hammerhead/0001-Overclock.patch" #2.26Ghz -> 2.95Ghz =+2.76Ghz XXX: Untested! -#enter "kernel/lge/mako" -#patch -p1 < $patches"android_kernel_lge_mako/0001-OverUnderClock.patch" #384Mhz -> 81Mhz, 1.51Ghz -> 1.94Ghz =+1.72Ghz XXX: Disabled due to excessive thermal throttling +enter "kernel/lge/mako" +patch -p1 < $patches"android_kernel_lge_mako/0001-Overclock.patch" +patch -p1 < $patches"android_kernel_lge_mako/0002-Overclock.patch" +patch -p1 < $patches"android_kernel_lge_mako/0003-Overclock.patch" +patch -p1 < $patches"android_kernel_lge_mako/0004-Overclock.patch" +patch -p1 < $patches"android_kernel_lge_mako/0005-Overclock.patch" +echo "CONFIG_LOW_CPUCLOCKS=y" >> arch/arm/configs/lineageos_mako_defconfig #384Mhz -> 81Mhz +echo "CONFIG_CPU_OVERCLOCK=y" >> arch/arm/configs/lineageos_mako_defconfig #1.51Ghz -> 1.7Ghz =+0.90Ghz +#echo "CPU_OVERCLOCK_ULTRA=y" >> arch/arm/configs/lineageos_mako_defconfig #1.51Ghz -> 1.94Ghz =+1.72Ghz XXX: Causes excessive throttling enter "kernel/lge/msm8992" patch -p1 < $patches"android_kernel_common_msm8992/0001-Overclock.patch"