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15.1: More aux work on rebase

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This commit is contained in:
Tad 2018-02-12 04:00:28 -05:00
parent 96edc2acc6
commit 4ee1a52cef
20 changed files with 4112 additions and 40 deletions
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307
Patches/LineageOS-15.1/android_kernel_common_msm8992/0001-Overclock.patch Normal file
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@ -0,0 +1,307 @@
From df33b6042093a177e2ef593f2d271dd33e1e251c Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Tue, 3 Nov 2015 21:21:34 -0500
Subject: [PATCH] msm8992 initial overclocking
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 30 ++++++++++++--------
arch/arm/boot/dts/qcom/msm8992.dtsi | 40 +++++++++++++++++++-------
drivers/clk/qcom/clock-cpu-8994.c | 8 +++---
drivers/cpufreq/qcom-cpufreq.c | 41 +++++++++++++++++++++++++++
4 files changed, 93 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index d5f68601759..23b23ba4e1a 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -605,7 +605,7 @@
regulator-name = "apc0_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <10>;
+ regulator-max-microvolt = <12>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1180000>;
qcom,cpr-voltage-floor = <640000 700000 800000 850000>;
@@ -669,15 +669,15 @@
qcom,cpr-init-voltage-ref = <900000 900000 1000000 1230000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 1 2 2 3 3 4 4 4 4>;
+ qcom,cpr-corner-map = <1 1 2 2 3 3 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 800000 800000 900000 900000
1000000 1000000 1115000 1115000
- 1180000 1180000>;
+ 1180000 1180000 1180000 1180000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 655000 700000 735000
800000 835000 850000 875000
- 950000 1000000>;
+ 950000 1000000 1000000 1000000>;
qcom,cpr-fuse-version-map =
<0 0xffffffff 0 0 0 0 0>,
<0 0xffffffff 1 0 0 0 0>,
@@ -759,10 +759,12 @@
<7 864000000>,
<8 960000000>,
<9 1248000000>,
- <10 1440000000>;
+ <10 1440000000>,
+ <11 1536000000>,
+ <12 1632000000>;
qcom,cpr-speed-bin-max-corners =
<0 0 2 4 6 9>,
- <1 0 2 4 6 10>;
+ <1 0 2 4 6 12>;
qcom,cpr-enable;
};
@@ -774,7 +776,7 @@
regulator-name = "apc1_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <15>;
+ regulator-max-microvolt = <17>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1180000>;
qcom,cpr-voltage-floor = <640000 640000 745000 850000>;
@@ -841,17 +843,19 @@
qcom,cpr-init-voltage-ref = <900000 900000 1000000 1230000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4>;
+ qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 900000 900000 900000 900000
900000 1000000 1000000 1000000
1115000 1115000 1115000 1115000
- 1115000 1115000 1180000>;
+ 1115000 1115000 1180000 1180000
+ 1180000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 640000 665000 690000
735000 745000 770000 785000
850000 860000 880000 900000
- 920000 935000 1000000>;
+ 920000 935000 1000000 1000000
+ 1000000>;
qcom,cpr-fuse-version-map =
<0xffffffff 0xffffffff 0 4 4 4 4>,
<0xffffffff 0xffffffff 1 4 4 4 4>,
@@ -908,9 +912,11 @@
<12 1536000000>,
<13 1632000000>,
<14 1689600000>,
- <15 1824000000>;
+ <15 1824000000>,
+ <16 1958400000>,
+ <17 2016000000>;
qcom,cpr-speed-bin-max-corners =
- <0xFFFFFFFF 0 1 5 8 15>;
+ <0xFFFFFFFF 0 1 5 8 17>;
qcom,cpr-enable;
};
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 5ba420c5b9c..8892b569694 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -852,7 +852,9 @@
< 787200 3509 >,
< 864000 4173 >,
< 960000 5271 >,
- < 1440000 7102 >;
+ < 1440000 7102 >,
+ < 1536000 7102 >,
+ < 1632000 7102 >;
cpu-to-dev-map-4 =
< 384000 1525 >,
< 633600 2288 >,
@@ -860,16 +862,22 @@
< 864000 4173 >,
< 960000 5271 >,
< 1344000 5928 >,
- < 1824000 7102 >;
+ < 1824000 7102 >,
+ < 1958400 7102 >,
+ < 2016000 7102 >;
};
mincpubw-cpufreq {
target-dev = <&mincpubw>;
cpu-to-dev-map-0 =
- < 1440000 1525 >;
+ < 1440000 1525 >,
+ < 1536000 1525 >,
+ < 1632000 1525 >;
cpu-to-dev-map-4 =
< 1689600 1525 >,
- < 1824000 5928 >;
+ < 1824000 1525 >,
+ < 1958400 1525 >,
+ < 2016000 5928 >;
};
cci-cpufreq {
@@ -880,7 +888,9 @@
< 787200 384000 >,
< 864000 556800 >,
< 960000 729600 >,
- < 1440000 787200 >;
+ < 1440000 787200 >,
+ < 1536000 787200 >,
+ < 1632000 787200 >;
cpu-to-dev-map-4 =
< 384000 134400 >,
< 480000 300000 >,
@@ -888,7 +898,9 @@
< 768000 556800 >,
< 960000 600000 >,
< 1440000 729600 >,
- < 1824000 787200 >;
+ < 1824000 787200 >,
+ < 1958400 787200 >,
+ < 2016000 787200 >;
};
};
@@ -915,7 +927,9 @@
< 864000 >,
< 960000 >,
< 1248000 >,
- < 1440000 >;
+ < 1440000 >,
+ < 1536000 >,
+ < 1632000 >;
qcom,cpufreq-table-4 =
< 384000 >,
@@ -930,7 +944,9 @@
< 1536000 >,
< 1632000 >,
< 1689600 >,
- < 1824000 >;
+ < 1824000 >,
+ < 1958400 >,
+ < 2016000 >;
};
@@ -968,7 +984,9 @@
< 864000000 7>,
< 960000000 8>,
< 1248000000 9>,
- < 1440000000 10>;
+ < 1440000000 10>,
+ < 1536000000 11>,
+ < 1632000000 12>;
qcom,a57-speedbin0-v0 =
< 0 0>,
< 384000000 5>,
@@ -983,7 +1001,9 @@
< 1536000000 12>,
< 1632000000 13>,
< 1689600000 14>,
- < 1824000000 15>;
+ < 1824000000 15>,
+ < 1958400000 16>,
+ < 2016000000 17>;
qcom,cci-speedbin0-v0 =
< 0 0>,
< 134400000 2>,
diff --git a/drivers/clk/qcom/clock-cpu-8994.c b/drivers/clk/qcom/clock-cpu-8994.c
index 7928f2ec0ca..351a66d4469 100644
--- a/drivers/clk/qcom/clock-cpu-8994.c
+++ b/drivers/clk/qcom/clock-cpu-8994.c
@@ -191,13 +191,13 @@ static struct pll_clk a57_pll0 = {
.test_ctl_lo_val = 0x00010000,
},
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll0",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll0.c),
},
};
@@ -229,13 +229,13 @@ static struct pll_clk a57_pll1 = {
/* Necessary since we'll be setting a rate before handoff on V1 */
.src_rate = 19200000,
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll1",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll1.c),
},
};
diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
index e30b0cb7483..dd3a5898597 100644
--- a/drivers/cpufreq/qcom-cpufreq.c
+++ b/drivers/cpufreq/qcom-cpufreq.c
@@ -31,6 +31,40 @@
static DEFINE_MUTEX(l2bw_lock);
+static unsigned long arg_cpu_max_a53 = 1440000;
+
+static int __init cpufreq_read_cpu_max_a53(char *cpu_max_a53)
+{
+ unsigned long ui_khz;
+ int ret;
+
+ ret = kstrtoul(cpu_max_a53, 0, &ui_khz);
+ if (ret)
+ return -EINVAL;
+
+ arg_cpu_max_a53 = ui_khz;
+ printk("cpu_max_a53=%lu\n", arg_cpu_max_a53);
+ return ret;
+}
+__setup("cpu_max_a53=", cpufreq_read_cpu_max_a53);
+
+static unsigned long arg_cpu_max_a57 = 1824000;
+
+static int __init cpufreq_read_cpu_max_a57(char *cpu_max_a57)
+{
+ unsigned long ui_khz;
+ int ret;
+
+ ret = kstrtoul(cpu_max_a57, 0, &ui_khz);
+ if (ret)
+ return -EINVAL;
+
+ arg_cpu_max_a57 = ui_khz;
+ printk("cpu_max_a57=%lu\n", arg_cpu_max_a57);
+ return ret;
+}
+__setup("cpu_max_a57=", cpufreq_read_cpu_max_a57);
+
static struct clk *cpu_clk[NR_CPUS];
static struct clk *l2_clk;
static DEFINE_PER_CPU(struct cpufreq_frequency_table *, freq_table);
@@ -364,6 +398,13 @@ static struct cpufreq_frequency_table *cpufreq_parse_dt(struct device *dev,
if (i > 0 && f <= ftbl[i-1].frequency)
break;
+ //Custom max freq
+ if ((cpu < 4 && f > arg_cpu_max_a53) ||
+ (cpu >= 4 && f > arg_cpu_max_a57)) {
+ nf = i;
+ break;
+ }
+
ftbl[i].driver_data = i;
ftbl[i].frequency = f;
}

47
Patches/LineageOS-15.1/android_kernel_common_msm8992/0002-Overclock.patch Normal file
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@ -0,0 +1,47 @@
From a7d2988f5ec81cd5e456eddba110d0ef1f809e50 Mon Sep 17 00:00:00 2001
From: Dan Sneddon <dsneddon@codeaurora.org>
Date: Fri, 27 Mar 2015 16:02:02 -0600
Subject: [PATCH] ARM: dts: msm: Adjust SPDM params on 8992
The current SPDM parameters cause a power increase
on 8992. This patch adjusts those parameters to
eliminate the negative power impact.
Change-Id: Ibdfaaf4cb50c346b6433a4a7dc910713bce8125f
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
---
arch/arm/boot/dts/qcom/msm8992-bus.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-bus.dtsi b/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
index 3efc2047d4a..e7b83cc11c0 100644
--- a/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
@@ -1516,8 +1516,8 @@
clocks = <&clock_cpu clk_cci_clk>;
qcom,bw-upstep = <1000>;
- qcom,bw-dwnstep = <1000>;
- qcom,max-vote = <10000>;
+ qcom,bw-dwnstep = <5000>;
+ qcom,max-vote = <5000>;
qcom,up-step-multp = <2>;
qcom,spdm-interval = <100>;
@@ -1527,14 +1527,14 @@
qcom,bucket-size = <8>;
/*max pl1 freq, max pl2 freq*/
- qcom,pl-freqs = <140000000 160000000>;
+ qcom,pl-freqs = <280000000 350000000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
qcom,reject-rate = <5000 5000 5000 5000 5000 5000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
qcom,response-time-us = <10000 10000 10000 10000 3000 3000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
- qcom,cci-response-time-us = <10000 10000 10000 10000 1000 1000>;
+ qcom,cci-response-time-us = <10000 10000 10000 10000 3000 3000>;
qcom,max-cci-freq = <787000000>;
};

43
Patches/LineageOS-15.1/android_kernel_common_msm8992/0003-Overclock.patch Normal file
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@ -0,0 +1,43 @@
From a288adcbf6ed14fccaa7726159b01eb9fcd74dc7 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Mon, 21 Nov 2016 21:40:09 -0500
Subject: [PATCH] msm8992: bump oc voltages
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index 23b23ba4e1a..19a3c1ca720 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -673,11 +673,11 @@
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 800000 800000 900000 900000
1000000 1000000 1115000 1115000
- 1180000 1180000 1180000 1180000>;
+ 1180000 1180000 1180000 1200000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 655000 700000 735000
800000 835000 850000 875000
- 950000 1000000 1000000 1000000>;
+ 950000 1000000 1000000 1100000>;
qcom,cpr-fuse-version-map =
<0 0xffffffff 0 0 0 0 0>,
<0 0xffffffff 1 0 0 0 0>,
@@ -849,13 +849,13 @@
900000 1000000 1000000 1000000
1115000 1115000 1115000 1115000
1115000 1115000 1180000 1180000
- 1180000>;
+ 1200000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 640000 665000 690000
735000 745000 770000 785000
850000 860000 880000 900000
920000 935000 1000000 1000000
- 1000000>;
+ 1100000>;
qcom,cpr-fuse-version-map =
<0xffffffff 0xffffffff 0 4 4 4 4>,
<0xffffffff 0xffffffff 1 4 4 4 4>,

32
Patches/LineageOS-15.1/android_kernel_common_msm8992/0004-Overclock.patch Normal file
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@ -0,0 +1,32 @@
From 1be9e1c5a09b3645e47a82ca199bf7153b7ffc35 Mon Sep 17 00:00:00 2001
From: Mathieu Maret <mmaret@genymobile.com>
Date: Wed, 4 Nov 2015 15:21:55 +0100
Subject: [PATCH] arm:dt:msm8994 Correct regulator timming
Documentation describe slew-rate as "time in us it takes for the regulator to change votlage value in one step".
2s seems a lot and qpnp-lab-slew-rate is only 5000us.
So correct it as if a 1000 factor was added.
This reduce the kernel boot time of the karin windy by 80s
Tested on karin windy only
Signed-off-by: Mathieu Maret <mmaret@genymobile.com>
Signed-off-by: mydongistiny <jaysonedson@gmail.com>
Signed-off-by: Joe Maples <joe@frap129.org>
---
arch/arm/boot/dts/qcom/msm-pmi8994.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
index 1303ba6a27b..de8259a53a7 100644
--- a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
@@ -459,7 +459,7 @@
qcom,qpnp-ibb-min-voltage = <1400000>;
qcom,qpnp-ibb-step-size = <100000>;
- qcom,qpnp-ibb-slew-rate = <2000000>;
+ qcom,qpnp-ibb-slew-rate = <2000>;
qcom,qpnp-ibb-use-default-voltage;
qcom,qpnp-ibb-init-voltage = <5500000>;
qcom,qpnp-ibb-init-amoled-voltage = <4000000>;

69
Patches/LineageOS-15.1/android_kernel_common_msm8992/0005-Overclock.patch Normal file
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@ -0,0 +1,69 @@
From 2368a976be94becdac216b4a09919010fd78b7cb Mon Sep 17 00:00:00 2001
From: Andrew Miyaguchi <XDleader555@gmail.com>
Date: Fri, 28 Jul 2017 16:34:20 -0700
Subject: [PATCH] arm/dts: msm8992: Add clock-frequency property
This commit will remove the following error message at boot
[0.062725,0] /cpus/cpu@0: Missing clock-frequency property
[0.062741,0] /cpus/cpu@1: Missing clock-frequency property
[0.062754,0] /cpus/cpu@2: Missing clock-frequency property
[0.062768,0] /cpus/cpu@3: Missing clock-frequency property
[0.062783,0] /cpus/cpu@4: Missing clock-frequency property
[0.062798,0] /cpus/cpu@5: Missing clock-frequency property
---
arch/arm/boot/dts/qcom/msm8992.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 38998c1b538..da44d9c5c61 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -75,6 +75,7 @@
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x0>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc0>;
@@ -110,6 +111,7 @@
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x1>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc1>;
@@ -139,6 +141,7 @@
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x2>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc2>;
@@ -168,6 +171,7 @@
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x3>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc3>;
@@ -197,6 +201,7 @@
CPU4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a57";
+ clock-frequency = <1824000000>;
reg = <0x100>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc4>;
@@ -236,6 +241,7 @@
CPU5: cpu@5 {
device_type = "cpu";
compatible = "arm,cortex-a57";
+ clock-frequency = <1824000000>;
reg = <0x101>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc5>;

32
Patches/LineageOS-15.1/android_kernel_common_msm8992/0006-Overclock.patch Normal file
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@ -0,0 +1,32 @@
From 813c7c2c64746a1960274b4d1d6277ca01350c67 Mon Sep 17 00:00:00 2001
From: Francisco Franco <franciscofranco.1990@gmail.com>
Date: Thu, 6 Jul 2017 13:02:58 +0000
Subject: [PATCH] bullhead: don't hotplug the perf cluster on BCL event, it
destroys performance and don't throttle so hard
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
---
arch/arm/boot/dts/qcom/msm8992.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index da44d9c5c61..9ecfb89ebbe 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -2754,13 +2754,13 @@
compatible = "qcom,bcl";
qcom,bcl-enable;
qcom,bcl-framework-interface;
- qcom,bcl-hotplug-list = <&CPU4 &CPU5>;
+ /delete-property/ qcom,bcl-hotplug-list;
+ /delete-property/ qcom,bcl-soc-hotplug-list;
qcom,bcl-freq-control-list = <&CPU4 &CPU5>;
- qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5>;
qcom,ibat-monitor {
qcom,low-threshold-uamp = <3400000>;
qcom,high-threshold-uamp = <4200000>;
- qcom,mitigation-freq-khz = <768000>;
+ qcom,mitigation-freq-khz = <960000>;
qcom,vph-high-threshold-uv = <3500000>;
qcom,vph-low-threshold-uv = <3300000>;
qcom,soc-low-threshold = <10>;

79
Patches/LineageOS-15.1/android_kernel_common_msm8992/0007-Overclock.patch Normal file
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@ -0,0 +1,79 @@
From c1f428064fed404f1e2271dda76ac98fcb0f714f Mon Sep 17 00:00:00 2001
From: Andrew Miyaguchi <XDleader555@gmail.com>
Date: Thu, 4 Jan 2018 01:32:30 -0800
Subject: [PATCH] ARM: dts: msm: add support for 302MHz on both A53/A57
Minimalistic edit without touching CCI frequencies
Also update regulator so voltage requests aren't rejected
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 6 +++---
arch/arm/boot/dts/qcom/msm8992.dtsi | 4 ++++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index 506a4542c50..20085cb75b5 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -549,7 +549,7 @@
compatible = "qcom,spm-regulator";
reg = <0x2900 0x100>;
regulator-name = "pm8994_s8";
- regulator-min-microvolt = <700000>;
+ regulator-min-microvolt = <640000>;
regulator-max-microvolt = <1180000>;
qcom,cpu-num = <0>;
};
@@ -750,7 +750,7 @@
qcom,cpr-voltage-scaling-factor-max = <0 0 2000 2000>;
qcom,cpr-quot-adjust-scaling-factor-max = <0 2000 2000 2000>;
qcom,cpr-corner-frequency-map =
- <1 300000000>,
+ <1 302400000>,
<2 384000000>,
<3 460800000>,
<4 600000000>,
@@ -899,7 +899,7 @@
qcom,cpr-quot-adjust-scaling-factor-max = <0 0 2000 2000>;
qcom,cpr-corner-frequency-map =
<1 300000000>, /* SVS Fmin for "SVS2" */
- <2 300000000>,
+ <2 302400000>,
<3 384000000>,
<4 480000000>,
<5 633600000>,
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 2f1c4399f19..7be0fa258ec 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -923,6 +923,7 @@
qcom,governor-per-policy;
qcom,cpufreq-table-0 =
+ < 302400 >,
< 384000 >,
< 460800 >,
< 600000 >,
@@ -936,6 +937,7 @@
< 1632000 >;
qcom,cpufreq-table-4 =
+ < 302400 >,
< 384000 >,
< 480000 >,
< 633600 >,
@@ -980,6 +982,7 @@
< 1248000000 9>;
qcom,a53-speedbin1-v0 =
< 0 0>,
+ < 302400000 1>,
< 384000000 2>,
< 460800000 3>,
< 600000000 4>,
@@ -993,6 +996,7 @@
< 1632000000 12>;
qcom,a57-speedbin0-v0 =
< 0 0>,
+ < 302400000 5>,
< 384000000 5>,
< 480000000 5>,
< 633600000 5>,

424
Patches/LineageOS-15.1/android_kernel_huawei_angler/0001-Overclock.patch Normal file
View File

@ -0,0 +1,424 @@
From e6fbf9568b5cfa91d9aa1006da1a799bd34f0c8f Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Tue, 3 Nov 2015 23:24:01 -0500
Subject: [PATCH] msm8994 overclocking
---
arch/arm/boot/dts/qcom/msm8994-regulator.dtsi | 172 +++++++++++++-------------
arch/arm/boot/dts/qcom/msm8994-v2.dtsi | 40 ++++--
drivers/clk/qcom/clock-cpu-8994.c | 8 +-
3 files changed, 122 insertions(+), 98 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8994-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8994-regulator.dtsi
index 93c9c647d9b..c245a55182f 100644
--- a/arch/arm/boot/dts/qcom/msm8994-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8994-regulator.dtsi
@@ -606,7 +606,7 @@
regulator-name = "apc0_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <13>;
+ regulator-max-microvolt = <15>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1180000>;
qcom,cpr-voltage-floor = <700000 700000 780000 835000>;
@@ -666,17 +666,17 @@
qcom,cpr-init-voltage-ref = <800000 900000 1000000 1225000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 2 2 2 3 3 3 4 4 4 4 4 4>;
+ qcom,cpr-corner-map = <1 2 2 2 3 3 3 4 4 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 900000 900000 900000 900000
1000000 1000000 1000000 1115000
1115000 1180000 1180000 1180000
- 1180000>;
+ 1180000 1180000 1180000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 700000 700000 700000 725000
780000 800000 825000 835000
850000 915000 970000 980000
- 1000000>;
+ 1000000 1000000 1000000>;
qcom,cpr-fuse-version-map =
<0xffffffff 0xffffffff 1 0 0 0 0>,
@@ -716,9 +716,11 @@
<10 1248000000>,
<11 1344000000>,
<12 1478400000>,
- <13 1555200000>;
+ <13 1555200000>,
+ <14 1632000000>,
+ <15 1708800000>;
qcom,cpr-speed-bin-max-corners =
- <0xFFFFFFFF 0 1 4 7 13>;
+ <0xFFFFFFFF 0 1 4 7 15>;
qcom,cpr-enable;
};
@@ -730,7 +732,7 @@
regulator-name = "apc1_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <17>;
+ regulator-max-microvolt = <19>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1225000>;
qcom,cpr-voltage-floor = <700000 700000 750000 835000>;
@@ -792,25 +794,25 @@
qcom,cpr-init-voltage-ref = <900000 900000 1000000 1225000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4 4 4>;
+ qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0 0 900000 900000 900000 900000 900000
1000000 1000000 1000000 1160000 1160000
1160000 1160000 1160000 1225000 1225000
- 1225000 1225000>,
+ 1225000 1225000 1225000 1225000>,
<1 0 900000 900000 900000 900000 900000
1000000 1000000 1000000 1160000 1160000
1160000 1160000 1160000 1225000 1225000
- 1225000 1225000>;
+ 1225000 1225000 1225000 1225000>;
qcom,cpr-voltage-floor-override =
<0 0 700000 700000 700000 700000 725000
750000 775000 795000 835000 860000
880000 895000 915000 935000 945000
- 950000 980000>,
+ 950000 980000 980000 980000>,
<1 0 700000 700000 700000 700000 725000
750000 775000 795000 835000 860000
880000 895000 915000 935000 945000
- 950000 980000>;
+ 950000 980000 980000 980000>;
qcom,cpr-fuse-version-map =
<0 0xffffffff 1 6 6 6 6>,
@@ -848,90 +850,90 @@
qcom,cpr-cpus = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment =
/* 1st fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 2nd fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 3rd fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 4th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 5th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 6th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 7th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
qcom,cpr-online-cpu-virtual-corner-quotient-adjustment =
/* 1st fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18) (-18) (-18)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18) (-18) (-18)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6) (-6) (-6)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 2nd fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18) (-18) (-18)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18) (-18) (-18)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6) (-6) (-6)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 3rd fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 4th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 5th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 6th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 7th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
qcom,cpr-online-cpu-init-voltage-as-ceiling;
qcom,cpr-voltage-scaling-factor-max = <0 0 2000 2000>;
@@ -953,9 +955,11 @@
<14 1728000000>,
<15 1766400000>,
<16 1824000000>,
- <17 1958400000>;
+ <17 1958400000>,
+ <18 2016000000>,
+ <19 2054400000>;
qcom,cpr-speed-bin-max-corners =
- <0 0 1 5 8 17>,
+ <0 0 1 5 8 19>,
<1 0 1 5 8 15>;
qcom,cpr-enable;
};
diff --git a/arch/arm/boot/dts/qcom/msm8994-v2.dtsi b/arch/arm/boot/dts/qcom/msm8994-v2.dtsi
index add83045413..3fea4251dfc 100644
--- a/arch/arm/boot/dts/qcom/msm8994-v2.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8994-v2.dtsi
@@ -83,7 +83,9 @@
< 1248000000 10>,
< 1344000000 11>,
< 1478400000 12>,
- < 1555200000 13>;
+ < 1555200000 13>,
+ < 1632000000 14>,
+ < 1708800000 15>;
qcom,a57-speedbin0-v0 =
< 0 0>,
< 384000000 5>,
@@ -99,7 +101,9 @@
< 1632000000 13>,
< 1728000000 14>,
< 1824000000 16>,
- < 1958400000 17>;
+ < 1958400000 17>,
+ < 2016000000 18>,
+ < 2054400000 19>;
qcom,a57-speedbin1-v0 =
< 0 0>,
< 384000000 5>,
@@ -146,7 +150,9 @@
< 1248000 >,
< 1344000 >,
< 1478400 >,
- < 1555200 >;
+ < 1555200 >,
+ < 1632000 >,
+ < 1708800 >;
qcom,cpufreq-table-4 =
< 384000 >,
@@ -162,7 +168,9 @@
< 1632000 >,
< 1728000 >,
< 1824000 >,
- < 1958400 >;
+ < 1958400 >,
+ < 2016000 >,
+ < 2054400 >;
};
&devfreq_cpufreq {
@@ -178,7 +186,9 @@
< 1248000 7904 >,
< 1344000 9887 >,
< 1478400 11863 >,
- < 1555200 11863 >;
+ < 1555200 11863 >,
+ < 1632000 11863 >,
+ < 1708800 11863 >;
cpu-to-dev-map-4 =
< 384000 1525 >,
< 480000 2288 >,
@@ -193,7 +203,9 @@
< 1632000 9887 >,
< 1728000 9887 >,
< 1824000 11863 >,
- < 1958400 11863 >;
+ < 1958400 11863 >,
+ < 2016000 11863 >,
+ < 2054400 11863 >;
};
mincpubw-cpufreq {
@@ -209,7 +221,9 @@
< 1248000 1525 >,
< 1344000 1525 >,
< 1478400 1525 >,
- < 1555200 1525 >;
+ < 1555200 1525 >,
+ < 1632000 1525 >,
+ < 1708800 1525 >;
cpu-to-dev-map-4 =
< 384000 1525 >,
< 480000 1525 >,
@@ -224,7 +238,9 @@
< 1632000 1525 >,
< 1728000 1525 >,
< 1824000 1525 >,
- < 1958400 7904 >;
+ < 1958400 7904 >,
+ < 2016000 7904 >,
+ < 2054400 7904 >;
};
cci-cpufreq {
@@ -239,7 +255,9 @@
< 1248000 729600 >,
< 1344000 787200 >,
< 1478400 787200 >,
- < 1555200 787200 >;
+ < 1555200 787200 >,
+ < 1632000 787200 >,
+ < 1708800 787200 >;
cpu-to-dev-map-4 =
< 384000 300000 >,
< 480000 300000 >,
@@ -254,7 +272,9 @@
< 1632000 787200 >,
< 1728000 787200 >,
< 1824000 787200 >,
- < 1958400 787200 >;
+ < 1958400 787200 >,
+ < 2016000 787200 >,
+ < 2054400 787200 >;
};
};
diff --git a/drivers/clk/qcom/clock-cpu-8994.c b/drivers/clk/qcom/clock-cpu-8994.c
index 7928f2ec0ca..351a66d4469 100644
--- a/drivers/clk/qcom/clock-cpu-8994.c
+++ b/drivers/clk/qcom/clock-cpu-8994.c
@@ -191,13 +191,13 @@ static struct pll_clk a57_pll0 = {
.test_ctl_lo_val = 0x00010000,
},
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll0",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll0.c),
},
};
@@ -229,13 +229,13 @@ static struct pll_clk a57_pll1 = {
/* Necessary since we'll be setting a rate before handoff on V1 */
.src_rate = 19200000,
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll1",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll1.c),
},
};

280
Patches/LineageOS-15.1/android_kernel_lge_g3/0001-Overclock.patch Normal file
View File

@ -0,0 +1,280 @@
From 74c64c5ec0f3ade9f3938b9e8634f85c77daeb42 Mon Sep 17 00:00:00 2001
From: Tectas <adrian.stoeckl@gmail.com>
Date: Thu, 23 Oct 2014 15:41:10 +0200
Subject: [PATCH] arch/arm/boot/dts: Overclocking up 2.7 Ghz
---
arch/arm/boot/dts/msm8974-regulator.dtsi | 8 +--
arch/arm/boot/dts/msm8974.dtsi | 6 +-
arch/arm/boot/dts/msm8974pro.dtsi | 96 ++++++++++++++++++++++++++------
3 files changed, 89 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974-regulator.dtsi b/arch/arm/boot/dts/msm8974-regulator.dtsi
index d5e8530a96f..9e29db34874 100644
--- a/arch/arm/boot/dts/msm8974-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974-regulator.dtsi
@@ -475,7 +475,7 @@
<0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -491,7 +491,7 @@
<0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -507,7 +507,7 @@
<0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -523,7 +523,7 @@
<0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 495117ff6e4..fc19c18e716 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1582,7 +1582,11 @@
< 1728000 1651200 6103 >,
< 1958400 1728000 7102 >,
< 2265600 1728000 7102 >,
- < 2457600 1728000 7102 >;
+ < 2457600 1728000 7102 >,
+ < 2534400 1728000 7102 >,
+ < 2611200 1728000 7102 >,
+ < 2688000 1728000 7102 >,
+ < 2764800 1728000 7102 >;
};
usb3: qcom,ssusb@f9200000 {
diff --git a/arch/arm/boot/dts/msm8974pro.dtsi b/arch/arm/boot/dts/msm8974pro.dtsi
index 3d03d9d2ee6..b01788d0020 100644
--- a/arch/arm/boot/dts/msm8974pro.dtsi
+++ b/arch/arm/boot/dts/msm8974pro.dtsi
@@ -1036,7 +1036,11 @@
< 2265600000 1085000 716 >,
< 2342400000 1100000 751 >,
< 2419200000 1115000 786 >,
- < 2457600000 1120000 802 >;
+ < 2457600000 1120000 802 >,
+ < 2534400000 1135000 837 >,
+ < 2611200000 1150000 872 >,
+ < 2688000000 1165000 907 >,
+ < 2764800000 1180000 942 >;
qcom,speed3-pvs1-bin-v1 =
< 0 0 0 >,
@@ -1070,7 +1074,11 @@
< 2265600000 1075000 716 >,
< 2342400000 1090000 751 >,
< 2419200000 1105000 786 >,
- < 2457600000 1110000 802 >;
+ < 2457600000 1110000 802 >,
+ < 2534400000 1125000 837 >,
+ < 2611200000 1140000 872 >,
+ < 2688000000 1155000 907 >,
+ < 2764800000 1170000 942 >;
qcom,speed3-pvs2-bin-v1 =
< 0 0 0 >,
@@ -1104,7 +1112,11 @@
< 2265600000 1065000 716 >,
< 2342400000 1080000 751 >,
< 2419200000 1095000 786 >,
- < 2457600000 1100000 802 >;
+ < 2457600000 1100000 802 >,
+ < 2534400000 1115000 837 >,
+ < 2611200000 1130000 872 >,
+ < 2688000000 1145000 907 >,
+ < 2764800000 1160000 942 >;
qcom,speed3-pvs3-bin-v1 =
< 0 0 0 >,
@@ -1138,7 +1150,11 @@
< 2265600000 1055000 716 >,
< 2342400000 1070000 751 >,
< 2419200000 1085000 786 >,
- < 2457600000 1090000 802 >;
+ < 2457600000 1090000 802 >,
+ < 2534400000 1105000 837 >,
+ < 2611200000 1120000 872 >,
+ < 2688000000 1135000 907 >,
+ < 2764800000 1150000 942 >;
qcom,speed3-pvs4-bin-v1 =
< 0 0 0 >,
@@ -1172,7 +1188,11 @@
< 2265600000 1045000 716 >,
< 2342400000 1060000 751 >,
< 2419200000 1075000 786 >,
- < 2457600000 1080000 802 >;
+ < 2457600000 1080000 802 >,
+ < 2534400000 1095000 837 >,
+ < 2611200000 1110000 872 >,
+ < 2688000000 1125000 907 >,
+ < 2764800000 1140000 942 >;
qcom,speed3-pvs5-bin-v1 =
< 0 0 0 >,
@@ -1206,7 +1226,11 @@
< 2265600000 1035000 716 >,
< 2342400000 1050000 751 >,
< 2419200000 1065000 786 >,
- < 2457600000 1070000 802 >;
+ < 2457600000 1070000 802 >,
+ < 2534400000 1085000 837 >,
+ < 2611200000 1100000 872 >,
+ < 2688000000 1115000 907 >,
+ < 2764800000 1130000 942 >;
qcom,speed3-pvs6-bin-v1 =
< 0 0 0 >,
@@ -1240,7 +1264,11 @@
< 2265600000 1025000 716 >,
< 2342400000 1040000 751 >,
< 2419200000 1055000 786 >,
- < 2457600000 1060000 802 >;
+ < 2457600000 1060000 802 >,
+ < 2534400000 1075000 837 >,
+ < 2611200000 1090000 872 >,
+ < 2688000000 1105000 907 >,
+ < 2764800000 1120000 942 >;
qcom,speed3-pvs7-bin-v1 =
< 0 0 0 >,
@@ -1274,7 +1302,11 @@
< 2265600000 1015000 716 >,
< 2342400000 1030000 751 >,
< 2419200000 1045000 786 >,
- < 2457600000 1050000 802 >;
+ < 2457600000 1050000 802 >,
+ < 2534400000 1065000 837 >,
+ < 2611200000 1080000 872 >,
+ < 2688000000 1095000 907 >,
+ < 2764800000 1110000 942 >;
qcom,speed3-pvs8-bin-v1 =
< 0 0 0 >,
@@ -1308,7 +1340,11 @@
< 2265600000 1005000 716 >,
< 2342400000 1020000 751 >,
< 2419200000 1035000 786 >,
- < 2457600000 1040000 802 >;
+ < 2457600000 1040000 802 >,
+ < 2534400000 1055000 837 >,
+ < 2611200000 1070000 872 >,
+ < 2688000000 1085000 907 >,
+ < 2764800000 1100000 942 >;
qcom,speed3-pvs9-bin-v1 =
< 0 0 0 >,
@@ -1342,7 +1378,11 @@
< 2265600000 995000 716 >,
< 2342400000 1010000 751 >,
< 2419200000 1025000 786 >,
- < 2457600000 1030000 802 >;
+ < 2457600000 1030000 802 >,
+ < 2534400000 1045000 837 >,
+ < 2611200000 1060000 872 >,
+ < 2688000000 1075000 907 >,
+ < 2764800000 1090000 942 >;
qcom,speed3-pvs10-bin-v1 =
< 0 0 0 >,
@@ -1376,7 +1416,11 @@
< 2265600000 985000 716 >,
< 2342400000 1000000 751 >,
< 2419200000 1015000 786 >,
- < 2457600000 1020000 802 >;
+ < 2457600000 1020000 802 >,
+ < 2534400000 1035000 837 >,
+ < 2611200000 1050000 872 >,
+ < 2688000000 1065000 907 >,
+ < 2764800000 1080000 942 >;
qcom,speed3-pvs11-bin-v1 =
< 0 0 0 >,
@@ -1410,7 +1454,11 @@
< 2265600000 975000 716 >,
< 2342400000 990000 751 >,
< 2419200000 1005000 786 >,
- < 2457600000 1010000 802 >;
+ < 2457600000 1010000 802 >,
+ < 2534400000 1025000 837 >,
+ < 2611200000 1040000 872 >,
+ < 2688000000 1055000 907 >,
+ < 2764800000 1070000 942 >;
qcom,speed3-pvs12-bin-v1 =
< 0 0 0 >,
@@ -1444,7 +1492,11 @@
< 2265600000 965000 716 >,
< 2342400000 980000 751 >,
< 2419200000 995000 786 >,
- < 2457600000 1000000 802 >;
+ < 2457600000 1000000 802 >,
+ < 2534400000 1015000 837 >,
+ < 2611200000 1030000 872 >,
+ < 2688000000 1045000 907 >,
+ < 2764800000 1060000 942 >;
qcom,speed3-pvs13-bin-v1 =
< 0 0 0 >,
@@ -1478,7 +1530,11 @@
< 2265600000 955000 716 >,
< 2342400000 970000 751 >,
< 2419200000 985000 786 >,
- < 2457600000 990000 802 >;
+ < 2457600000 990000 802 >,
+ < 2534400000 1005000 837 >,
+ < 2611200000 1020000 872 >,
+ < 2688000000 1035000 907 >,
+ < 2764800000 1050000 942 >;
qcom,speed3-pvs14-bin-v1 =
< 0 0 0 >,
@@ -1512,7 +1568,11 @@
< 2265600000 945000 716 >,
< 2342400000 960000 751 >,
< 2419200000 975000 786 >,
- < 2457600000 980000 802 >;
+ < 2457600000 980000 802 >,
+ < 2534400000 995000 837 >,
+ < 2611200000 1010000 872 >,
+ < 2688000000 1025000 907 >,
+ < 2764800000 1040000 942 >;
qcom,speed3-pvs15-bin-v1 =
< 0 0 0 >,
@@ -1546,7 +1606,11 @@
< 2265600000 935000 716 >,
< 2342400000 950000 751 >,
< 2419200000 965000 786 >,
- < 2457600000 970000 802 >;
+ < 2457600000 970000 802 >,
+ < 2534400000 985000 837 >,
+ < 2611200000 1000000 872 >,
+ < 2688000000 1015000 907 >,
+ < 2764800000 1030000 942 >;
};
i2c@f9928000 { /* BLSP-1 QUP-6 */

82
Patches/LineageOS-15.1/android_kernel_lge_g3/0002-Overclock.patch Normal file
View File

@ -0,0 +1,82 @@
From 2d16761887d7fb80da131b5cf38e32bcc94a3011 Mon Sep 17 00:00:00 2001
From: Tectas <adrian.stoeckl@gmail.com>
Date: Mon, 17 Nov 2014 21:21:08 +0100
Subject: [PATCH] arch/arm/boot/dts: Raise max microvolt at cpu for pm8941 and
pma8084
---
arch/arm/boot/dts/msm8974pro-pm8941.dtsi | 8 ++++----
arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974pro-pm8941.dtsi b/arch/arm/boot/dts/msm8974pro-pm8941.dtsi
index b5020789bbb..2c5dd3d4416 100644
--- a/arch/arm/boot/dts/msm8974pro-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-pm8941.dtsi
@@ -39,22 +39,22 @@
};
&krait0_vreg {
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,ldo-delta-voltage = <12500>;
};
&krait1_vreg {
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,ldo-delta-voltage = <12500>;
};
&krait2_vreg {
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,ldo-delta-voltage = <12500>;
};
&krait3_vreg {
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,ldo-delta-voltage = <12500>;
};
diff --git a/arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi b/arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi
index 433d466a3ee..8674dee3096 100644
--- a/arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi
@@ -492,7 +492,7 @@
<0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -508,7 +508,7 @@
<0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -524,7 +524,7 @@
<0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -540,7 +540,7 @@
<0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;

38
Patches/LineageOS-15.1/android_kernel_lge_g3/0003-Overclock.patch Normal file
View File

@ -0,0 +1,38 @@
From 74a364df2dfe05460cffd081ac3bab672faf346c Mon Sep 17 00:00:00 2001
From: Tectas <adrian.stoeckl@gmail.com>
Date: Thu, 20 Nov 2014 21:28:16 +0100
Subject: [PATCH] arch/arm/boot/dts: Add more frequencies for UC
---
arch/arm/boot/dts/msm8974.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index fc19c18e716..83ead25e266 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1569,6 +1569,7 @@
compatible = "qcom,msm-cpufreq";
qcom,cpufreq-table =
< 300000 300000 572 >,
+ < 345600 300000 572 >,
< 422400 422400 1144 >,
< 652800 499200 1525 >,
< 729600 576000 2342 >,
@@ -1579,9 +1580,16 @@
< 1267200 1267200 4684 >,
< 1497600 1497600 4684 >,
< 1574400 1574400 6103 >,
+ < 1651200 1574400 6103 >,
< 1728000 1651200 6103 >,
+ < 1804800 1651200 6103 >,
< 1958400 1728000 7102 >,
+ < 2035200 1728000 7102 >,
+ < 2112000 1728000 7102 >,
+ < 2188800 1728000 7102 >,
< 2265600 1728000 7102 >,
+ < 2342400 1728000 7102 >,
+ < 2419200 1728000 7102 >,
< 2457600 1728000 7102 >,
< 2534400 1728000 7102 >,
< 2611200 1728000 7102 >,

39
Patches/LineageOS-15.1/android_kernel_lge_g3/0004-Overclock.patch Normal file
View File

@ -0,0 +1,39 @@
From 52b1a7fd2f9379f703d0d9f368faba1e993c37b8 Mon Sep 17 00:00:00 2001
From: Tectas <adrian.stoeckl@gmail.com>
Date: Wed, 26 Nov 2014 09:36:19 +0100
Subject: [PATCH] arch/arm/boot/dts: Remove some UC steps for better
performance
---
arch/arm/boot/dts/msm8974.dtsi | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 83ead25e266..de83da943dd 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1569,7 +1569,6 @@
compatible = "qcom,msm-cpufreq";
qcom,cpufreq-table =
< 300000 300000 572 >,
- < 345600 300000 572 >,
< 422400 422400 1144 >,
< 652800 499200 1525 >,
< 729600 576000 2342 >,
@@ -1580,16 +1579,12 @@
< 1267200 1267200 4684 >,
< 1497600 1497600 4684 >,
< 1574400 1574400 6103 >,
- < 1651200 1574400 6103 >,
< 1728000 1651200 6103 >,
< 1804800 1651200 6103 >,
< 1958400 1728000 7102 >,
- < 2035200 1728000 7102 >,
< 2112000 1728000 7102 >,
< 2188800 1728000 7102 >,
- < 2265600 1728000 7102 >,
< 2342400 1728000 7102 >,
- < 2419200 1728000 7102 >,
< 2457600 1728000 7102 >,
< 2534400 1728000 7102 >,
< 2611200 1728000 7102 >,

757
Patches/LineageOS-15.1/android_kernel_lge_hammerhead/0001-Overclock.patch Normal file
View File

@ -0,0 +1,757 @@
From ec5d8918e9d3149ce489900f48d6e6ebd2fd5031 Mon Sep 17 00:00:00 2001
From: Paul Reioux <reioux@gmail.com>
Date: Sun, 20 Oct 2013 22:30:36 -0500
Subject: [PATCH 1/5] Voltage Control: initial voltage control for MSM
Snapdragon 800 SOC
Signed-off-by: Paul Reioux <reioux@gmail.com>
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/mach-msm/Kconfig | 6 +++++
arch/arm/mach-msm/acpuclock-krait.c | 48 +++++++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index ba5a33c..44db2ca 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1918,6 +1918,12 @@ config MSM_CPU_FREQ_MIN
endif # CPU_FREQ_MSM
+config CPU_VOLTAGE_TABLE
+ bool "Enable CPU Voltage Table via sysfs for adjustements"
+ default n
+ help
+ Krait User Votlage Control
+
config MSM_AVS_HW
bool "Enable Adaptive Voltage Scaling (AVS)"
default n
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 84e2fc1..c7eceb1 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -937,6 +937,54 @@ static void __init bus_init(const struct l2_level *l2_level)
dev_err(drv.dev, "initial bandwidth req failed (%d)\n", ret);
}
+#ifdef CONFIG_CPU_VOLTAGE_TABLE
+
+#define HFPLL_MIN_VDD 800000
+#define HFPLL_MAX_VDD 1350000
+
+ssize_t acpuclk_get_vdd_levels_str(char *buf) {
+
+ int i, len = 0;
+
+ if (buf) {
+ mutex_lock(&driver_lock);
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz; i++) {
+ /* updated to use uv required by 8x60 architecture - faux123 */
+ len += sprintf(buf + len, "%8lu: %8d\n", drv.acpu_freq_tbl[i].speed.khz,
+ drv.acpu_freq_tbl[i].vdd_core );
+ }
+
+ mutex_unlock(&driver_lock);
+ }
+ return len;
+}
+
+/* updated to use uv required by 8x60 architecture - faux123 */
+void acpuclk_set_vdd(unsigned int khz, int vdd_uv) {
+
+ int i;
+ unsigned int new_vdd_uv;
+
+ mutex_lock(&driver_lock);
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz; i++) {
+ if (khz == 0)
+ new_vdd_uv = min(max((unsigned int)(drv.acpu_freq_tbl[i].vdd_core + vdd_uv),
+ (unsigned int)HFPLL_MIN_VDD), (unsigned int)HFPLL_MAX_VDD);
+ else if ( drv.acpu_freq_tbl[i].speed.khz == khz)
+ new_vdd_uv = min(max((unsigned int)vdd_uv,
+ (unsigned int)HFPLL_MIN_VDD), (unsigned int)HFPLL_MAX_VDD);
+ else
+ continue;
+
+ drv.acpu_freq_tbl[i].vdd_core = new_vdd_uv;
+ }
+ pr_warn("faux123: user voltage table modified!\n");
+ mutex_unlock(&driver_lock);
+}
+#endif /* CONFIG_CPU_VOTALGE_TABLE */
+
#ifdef CONFIG_CPU_FREQ_MSM
static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
--
2.9.3
From 1e4ac53ff15efeaf4cb3998b9ba009095d582413 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Sat, 9 Nov 2013 00:17:33 -0500
Subject: [PATCH 2/5] Increase voltage limits
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/boot/dts/msm8974-regulator.dtsi | 8 ++++----
arch/arm/mach-msm/acpuclock-8974.c | 8 ++++----
arch/arm/mach-msm/acpuclock-krait.c | 4 ++--
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974-regulator.dtsi b/arch/arm/boot/dts/msm8974-regulator.dtsi
index 9de41f4..6a38980 100644
--- a/arch/arm/boot/dts/msm8974-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974-regulator.dtsi
@@ -477,7 +477,7 @@
<0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -493,7 +493,7 @@
<0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -509,7 +509,7 @@
<0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -525,7 +525,7 @@
<0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 694d783..8b7d74e 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -55,7 +55,7 @@ static struct scalable scalable[] __initdata = {
.hfpll_phys_base = 0xF908A000,
.l2cpmr_iaddr = 0x4501,
.sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait0", 1100000 },
+ .vreg[VREG_CORE] = { "krait0", 1200000 },
.vreg[VREG_MEM] = { "krait0_mem", 1050000 },
.vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -64,7 +64,7 @@ static struct scalable scalable[] __initdata = {
.hfpll_phys_base = 0xF909A000,
.l2cpmr_iaddr = 0x5501,
.sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait1", 1100000 },
+ .vreg[VREG_CORE] = { "krait1", 1200000 },
.vreg[VREG_MEM] = { "krait1_mem", 1050000 },
.vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
@@ -73,7 +73,7 @@ static struct scalable scalable[] __initdata = {
.hfpll_phys_base = 0xF90AA000,
.l2cpmr_iaddr = 0x6501,
.sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait2", 1100000 },
+ .vreg[VREG_CORE] = { "krait2", 1200000 },
.vreg[VREG_MEM] = { "krait2_mem", 1050000 },
.vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
@@ -82,7 +82,7 @@ static struct scalable scalable[] __initdata = {
.hfpll_phys_base = 0xF90BA000,
.l2cpmr_iaddr = 0x7501,
.sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait3", 1100000 },
+ .vreg[VREG_CORE] = { "krait3", 1200000 },
.vreg[VREG_MEM] = { "krait3_mem", 1050000 },
.vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index c7eceb1..2211ad3 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -939,8 +939,8 @@ static void __init bus_init(const struct l2_level *l2_level)
#ifdef CONFIG_CPU_VOLTAGE_TABLE
-#define HFPLL_MIN_VDD 800000
-#define HFPLL_MAX_VDD 1350000
+#define HFPLL_MIN_VDD 500000
+#define HFPLL_MAX_VDD 1200000
ssize_t acpuclk_get_vdd_levels_str(char *buf) {
--
2.9.3
From 28d7063d0b5a45d328633e4a59d20ac148f1fadd Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Sat, 9 Nov 2013 01:27:36 -0500
Subject: [PATCH 3/5] CPU overclocking
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/mach-msm/acpuclock-8974.c | 42 ++++++++++
arch/arm/mach-msm/acpuclock-krait.c | 148 +++++++++++++++++++++++++++++++++++-
2 files changed, 189 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 8b7d74e..cb878d9 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -710,6 +710,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs0[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1070000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1085000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1100000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1115000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1130000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1145000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1160000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1175000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1195000, 831 },
{ 0, { 0 } }
};
@@ -741,6 +747,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs1[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1090000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1105000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1120000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1135000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1150000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1165000, 831 },
{ 0, { 0 } }
};
@@ -772,6 +784,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs2[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1065000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1080000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1095000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1110000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1125000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1140000, 831 },
{ 0, { 0 } }
};
@@ -803,6 +821,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs3[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1040000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1070000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1085000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1100000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1115000, 831 },
{ 0, { 0 } }
};
@@ -834,6 +858,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs4[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1015000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1030000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1045000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1060000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1075000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1090000, 831 },
{ 0, { 0 } }
};
@@ -865,6 +895,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs5[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 990000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1020000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1035000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1050000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1065000, 831 },
{ 0, { 0 } }
};
@@ -896,6 +932,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs6[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 960000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 975000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 990000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1005000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1020000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1035000, 831 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 2211ad3..bcd3e44 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -45,6 +45,113 @@
#define PRI_SRC_SEL_HFPLL 1
#define PRI_SRC_SEL_HFPLL_DIV2 2
+
+/** elementalx defs **/
+static int uv_bin = 2;
+static uint32_t arg_max_oc0 = 2265600;
+static uint32_t arg_max_oc1 = 2265600;
+static uint32_t arg_max_oc2 = 2265600;
+static uint32_t arg_max_oc3 = 2265600;
+
+int pvs_number = 0;
+module_param(pvs_number, int, 0755);
+
+/* boot arg max_oc */
+static int __init cpufreq_read_arg_max_oc0(char *max_oc0)
+{
+ unsigned long ui_khz;
+ int err;
+ err = strict_strtoul(max_oc0, 0, &ui_khz);
+ if (err) {
+ arg_max_oc0 = 2265600;
+ printk(KERN_INFO "[elementalx]: max_oc0='%i'\n", arg_max_oc0);
+ return 1;
+ }
+
+ arg_max_oc0 = ui_khz;
+
+ return 0;
+}
+__setup("max_oc0=", cpufreq_read_arg_max_oc0);
+
+static int __init cpufreq_read_arg_max_oc1(char *max_oc1)
+{
+ unsigned long ui_khz;
+ int err;
+ err = strict_strtoul(max_oc1, 0, &ui_khz);
+ if (err) {
+ arg_max_oc1 = 2265600;
+ printk(KERN_INFO "[elementalx]: max_oc1='%i'\n", arg_max_oc1);
+ return 1;
+ }
+
+ arg_max_oc1 = ui_khz;
+
+ return 0;
+}
+__setup("max_oc1=", cpufreq_read_arg_max_oc1);
+
+static int __init cpufreq_read_arg_max_oc2(char *max_oc2)
+{
+ unsigned long ui_khz;
+ int err;
+ err = strict_strtoul(max_oc2, 0, &ui_khz);
+ if (err) {
+ arg_max_oc2 = 2265600;
+ printk(KERN_INFO "[elementalx]: max_oc2='%i'\n", arg_max_oc2);
+ return 1;
+ }
+
+ arg_max_oc2 = ui_khz;
+
+ return 0;
+}
+__setup("max_oc2=", cpufreq_read_arg_max_oc2);
+
+static int __init cpufreq_read_arg_max_oc3(char *max_oc3)
+{
+ unsigned long ui_khz;
+ int err;
+ err = strict_strtoul(max_oc3, 0, &ui_khz);
+ if (err) {
+ arg_max_oc3 = 2265600;
+ printk(KERN_INFO "[elementalx]: max_oc3='%i'\n", arg_max_oc3);
+ return 1;
+ }
+
+ arg_max_oc3 = ui_khz;
+
+ return 0;
+}
+__setup("max_oc3=", cpufreq_read_arg_max_oc3);
+
+static int __init get_uv_level(char *vdd_uv)
+{
+ if (strcmp(vdd_uv, "0") == 0) {
+ uv_bin = 0;
+ } else if (strcmp(vdd_uv, "1") == 0) {
+ uv_bin = 1;
+ } else if (strcmp(vdd_uv, "2") == 0) {
+ uv_bin = 2;
+ } else if (strcmp(vdd_uv, "3") == 0) {
+ uv_bin = 3;
+ } else if (strcmp(vdd_uv, "4") == 0) {
+ uv_bin = 4;
+ } else if (strcmp(vdd_uv, "5") == 0) {
+ uv_bin = 5;
+ } else if (strcmp(vdd_uv, "6") == 0) {
+ uv_bin = 6;
+ } else {
+ uv_bin = 0;
+ }
+ return 0;
+}
+
+__setup("vdd_uv=", get_uv_level);
+
+/** end elementalx defs **/
+
+
static DEFINE_MUTEX(driver_lock);
static DEFINE_SPINLOCK(l2_lock);
@@ -992,13 +1099,14 @@ static void __init cpufreq_table_init(void)
{
int cpu;
int freq_cnt = 0;
+ uint32_t limit_max_oc[4] = {arg_max_oc0, arg_max_oc1, arg_max_oc2, arg_max_oc3};
for_each_possible_cpu(cpu) {
int i;
/* Construct the freq_table tables from acpu_freq_tbl. */
for (i = 0, freq_cnt = 0; drv.acpu_freq_tbl[i].speed.khz != 0
&& freq_cnt < ARRAY_SIZE(*freq_table); i++) {
- if (drv.acpu_freq_tbl[i].use_for_scaling) {
+ if (drv.acpu_freq_tbl[i].speed.khz <= limit_max_oc[cpu]) {
freq_table[cpu][freq_cnt].index = freq_cnt;
freq_table[cpu][freq_cnt].frequency
= drv.acpu_freq_tbl[i].speed.khz;
@@ -1109,6 +1217,39 @@ static void __init krait_apply_vmin(struct acpu_level *tbl)
}
}
+static void apply_undervolting(void)
+{
+ if (uv_bin == 6) {
+ drv.acpu_freq_tbl[0].vdd_core = 625000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 5) {
+ drv.acpu_freq_tbl[0].vdd_core = 650000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 4) {
+ drv.acpu_freq_tbl[0].vdd_core = 675000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 3) {
+ drv.acpu_freq_tbl[0].vdd_core = 700000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 2) {
+ drv.acpu_freq_tbl[0].vdd_core = 725000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 1) {
+ drv.acpu_freq_tbl[0].vdd_core = 750000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+}
+
void __init get_krait_bin_format_a(void __iomem *base, struct bin_info *bin)
{
u32 pte_efuse = readl_relaxed(base);
@@ -1143,6 +1284,8 @@ void __init get_krait_bin_format_b(void __iomem *base, struct bin_info *bin)
}
bin->speed_valid = true;
+ pvs_number = bin->pvs;
+
/* Check PVS_BLOW_STATUS */
pte_efuse = readl_relaxed(base + 0x4);
bin->pvs_valid = !!(pte_efuse & BIT(21));
@@ -1229,6 +1372,9 @@ static void __init hw_init(void)
if (krait_needs_vmin())
krait_apply_vmin(drv.acpu_freq_tbl);
+ if (uv_bin)
+ apply_undervolting();
+
l2->hfpll_base = ioremap(l2->hfpll_phys_base, SZ_32);
BUG_ON(!l2->hfpll_base);
--
2.9.3
From cbc2f6c8893c773d4dbdf9d5f538f6b44a02baa4 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Sat, 9 Nov 2013 08:43:31 -0500
Subject: [PATCH 4/5] L2 cache and bus bandwidth overclocking
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/mach-msm/acpuclock-8974.c | 46 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-msm/acpuclock-krait.c | 2 +-
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index cb878d9..933bd0e 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -28,6 +28,8 @@
#define LVL_NOM RPM_REGULATOR_CORNER_NORMAL
#define LVL_HIGH RPM_REGULATOR_CORNER_SUPER_TURBO
+static int opt_bin = 0;
+
static struct hfpll_data hfpll_data __initdata = {
.mode_offset = 0x00,
.l_offset = 0x04,
@@ -257,6 +259,7 @@ static struct msm_bus_paths bw_level_tbl_v2[] __initdata = {
[6] = BW_MBPS(4912), /* At least 614 MHz on bus. */
[7] = BW_MBPS(6400), /* At least 800 MHz on bus. */
[8] = BW_MBPS(7448), /* At least 931 MHz on bus. */
+ [9] = BW_MBPS(8000), /* At least 1000 MHz on bus. */
};
static struct l2_level l2_freq_tbl_v2[] __initdata = {
@@ -283,6 +286,30 @@ static struct l2_level l2_freq_tbl_v2[] __initdata = {
{ }
};
+static struct l2_level l2_freq_tbl_v2_elementalx[] __initdata = {
+ [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
+ [1] = { { 345600, HFPLL, 2, 36 }, LVL_LOW, 950000, 1 },
+ [2] = { { 422400, HFPLL, 2, 44 }, LVL_LOW, 950000, 2 },
+ [3] = { { 499200, HFPLL, 2, 52 }, LVL_LOW, 950000, 3 },
+ [4] = { { 576000, HFPLL, 1, 30 }, LVL_LOW, 950000, 4 },
+ [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 4 },
+ [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 4 },
+ [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 4 },
+ [8] = { { 883200, HFPLL, 1, 46 }, LVL_NOM, 950000, 5 },
+ [9] = { { 960000, HFPLL, 1, 50 }, LVL_NOM, 950000, 5 },
+ [10] = { { 1036800, HFPLL, 1, 54 }, LVL_NOM, 950000, 5 },
+ [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 6 },
+ [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 6 },
+ [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 6 },
+ [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 6 },
+ [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 6 },
+ [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 6 },
+ [17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 7 },
+ [18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 7 },
+ [19] = { { 1804800, HFPLL, 1, 94 }, LVL_HIGH, 1050000, 9 },
+ { }
+};
+
static struct acpu_level acpu_freq_tbl_2g_pvs0[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 815000, 73 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(1), 825000, 85 },
@@ -1003,6 +1030,20 @@ static struct acpuclk_krait_params acpuclk_8974_params __initdata = {
.stby_khz = 300000,
};
+static int __init get_opt_level(char *l2_opt)
+{
+ if (strcmp(l2_opt, "0") == 0) {
+ opt_bin = 0;
+ } else if (strcmp(l2_opt, "1") == 0) {
+ opt_bin = 1;
+ } else {
+ opt_bin = 0;
+ }
+ return 0;
+}
+
+__setup("l2_opt=", get_opt_level);
+
static void __init apply_v1_l2_workaround(void)
{
static struct l2_level resticted_l2_tbl[] __initdata = {
@@ -1042,6 +1083,11 @@ static int __init acpuclk_8974_probe(struct platform_device *pdev)
apply_v1_l2_workaround();
}
+ if (opt_bin == 1) {
+ acpuclk_8974_params.l2_freq_tbl = l2_freq_tbl_v2_elementalx;
+ acpuclk_8974_params.l2_freq_tbl_size = sizeof(l2_freq_tbl_v2_elementalx);
+ }
+
return acpuclk_krait_init(&pdev->dev, &acpuclk_8974_params);
}
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index bcd3e44..a1c8fbb 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -47,7 +47,7 @@
/** elementalx defs **/
-static int uv_bin = 2;
+static int uv_bin = 0;
static uint32_t arg_max_oc0 = 2265600;
static uint32_t arg_max_oc1 = 2265600;
static uint32_t arg_max_oc2 = 2265600;
--
2.9.3
From bfd08d2e2a997ac4f5b6e8353be663472643b746 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Mon, 11 Nov 2013 00:42:12 -0500
Subject: [PATCH 5/5] More overclocking options
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/mach-msm/acpuclock-8974.c | 50 ++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 933bd0e..b436816 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -310,6 +310,29 @@ static struct l2_level l2_freq_tbl_v2_elementalx[] __initdata = {
{ }
};
+static struct l2_level l2_freq_tbl_v2_ultra[] __initdata = {
+ [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
+ [1] = { { 345600, HFPLL, 2, 36 }, LVL_LOW, 950000, 1 },
+ [2] = { { 422400, HFPLL, 2, 44 }, LVL_LOW, 950000, 2 },
+ [3] = { { 499200, HFPLL, 2, 52 }, LVL_LOW, 950000, 3 },
+ [4] = { { 576000, HFPLL, 1, 30 }, LVL_LOW, 950000, 4 },
+ [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 4 },
+ [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 4 },
+ [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 4 },
+ [8] = { { 883200, HFPLL, 1, 46 }, LVL_NOM, 950000, 5 },
+ [9] = { { 960000, HFPLL, 1, 50 }, LVL_NOM, 950000, 5 },
+ [10] = { { 1036800, HFPLL, 1, 54 }, LVL_NOM, 950000, 5 },
+ [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 6 },
+ [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 6 },
+ [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 6 },
+ [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 6 },
+ [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 6 },
+ [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 6 },
+ [17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 7 },
+ [18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 7 },
+ [19] = { { 1920000, HFPLL, 1, 100 }, LVL_HIGH, 1050000, 9 },
+ { }
+};
static struct acpu_level acpu_freq_tbl_2g_pvs0[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 815000, 73 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(1), 825000, 85 },
@@ -743,6 +766,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs0[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1160000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1175000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1195000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1195000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1195000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1195000, 897 },
{ 0, { 0 } }
};
@@ -780,6 +806,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs1[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1135000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1150000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1165000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1180000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1195000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1195000, 897 },
{ 0, { 0 } }
};
@@ -817,6 +846,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs2[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1110000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1125000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1140000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1165000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1180000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1195000, 897 },
{ 0, { 0 } }
};
@@ -854,6 +886,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs3[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1085000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1100000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1115000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1130000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1145000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1160000, 897 },
{ 0, { 0 } }
};
@@ -891,6 +926,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs4[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1060000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1075000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1090000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1105000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1120000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1135000, 897 },
{ 0, { 0 } }
};
@@ -928,6 +966,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs5[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1035000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1050000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1065000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1080000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1095000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1110000, 897 },
{ 0, { 0 } }
};
@@ -965,6 +1006,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs6[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1005000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1020000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1035000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1050000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1065000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1080000, 897 },
{ 0, { 0 } }
};
@@ -1036,6 +1080,8 @@ static int __init get_opt_level(char *l2_opt)
opt_bin = 0;
} else if (strcmp(l2_opt, "1") == 0) {
opt_bin = 1;
+ } else if (strcmp(l2_opt, "2") == 0) {
+ opt_bin = 2;
} else {
opt_bin = 0;
}
@@ -1087,6 +1133,10 @@ static int __init acpuclk_8974_probe(struct platform_device *pdev)
acpuclk_8974_params.l2_freq_tbl = l2_freq_tbl_v2_elementalx;
acpuclk_8974_params.l2_freq_tbl_size = sizeof(l2_freq_tbl_v2_elementalx);
}
+ if (opt_bin == 2) {
+ acpuclk_8974_params.l2_freq_tbl = l2_freq_tbl_v2_ultra;
+ acpuclk_8974_params.l2_freq_tbl_size = sizeof(l2_freq_tbl_v2_ultra);
+ }
return acpuclk_krait_init(&pdev->dev, &acpuclk_8974_params);
}
--
2.9.3

490
Patches/LineageOS-15.1/android_kernel_motorola_msm8916/0001-Overclock.patch Normal file
View File

@ -0,0 +1,490 @@
From 0f5855241796b323b7a71b0c2f02df15b69fbbe1 Mon Sep 17 00:00:00 2001
From: nguyenquangduc2000 <nguyenquangduc2000@gmail.com>
Date: Thu, 7 Jul 2016 15:08:14 +0700
Subject: [PATCH] Overclock 1.9Ghz/720Mhz
---
arch/arm/boot/dts/qcom/msm8916-gpu.dtsi | 114 ++++++++++++++++++------
arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi | 36 +++++++-
arch/arm/boot/dts/qcom/msm8916-regulator.dtsi | 27 +++---
arch/arm/boot/dts/qcom/msm8916.dtsi | 40 +++++++--
drivers/clk/qcom/clock-gcc-8916.c | 35 +++++---
5 files changed, 195 insertions(+), 57 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi b/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
index 84e183f..d9269d7 100644
--- a/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
@@ -27,9 +27,8 @@
qcom,chipid = <0x03000600>;
- qcom,initial-pwrlevel = <1>;
-
- /* Idle Timeout */
+ qcom,initial-pwrlevel = <8>;
+ /* Idle Timeout = msec */
qcom,idle-timeout = <80>;
qcom,strtstp-sleepwake;
@@ -82,30 +81,59 @@
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <720000000>;
+ qcom,bus-freq = <3>;
+ };
- qcom,gpu-pwrlevel@0 {
- reg = <0>;
- qcom,gpu-freq = <400000000>;
- qcom,bus-freq = <3>;
- };
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <3>;
+ };
- qcom,gpu-pwrlevel@1 {
- reg = <1>;
- qcom,gpu-freq = <310000000>;
- qcom,bus-freq = <2>;
- };
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <550000000>;
+ qcom,bus-freq = <3>;
+ };
- qcom,gpu-pwrlevel@2 {
- reg = <2>;
- qcom,gpu-freq = <200000000>;
- qcom,bus-freq = <1>;
- };
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <475000000>;
+ qcom,bus-freq = <3>;
+ };
- qcom,gpu-pwrlevel@3 {
- reg = <3>;
- qcom,gpu-freq = <19200000>;
- qcom,bus-freq = <0>;
- };
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <3>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <310000000>;
+ qcom,bus-freq = <2>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <200000000>;
+ qcom,bus-freq = <1>;
+ };
+
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <100000000>;
+ qcom,bus-freq = <1>;
+ };
+
+ qcom,gpu-pwrlevel@8 {
+ reg = <8>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ };
};
/* Speed levels */
qcom,gpu-speed-config@2 {
@@ -129,24 +157,54 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
- qcom,gpu-freq = <465000000>;
+ qcom,gpu-freq = <720000000>;
qcom,bus-freq = <3>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
- qcom,gpu-freq = <310000000>;
- qcom,bus-freq = <2>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <3>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
- qcom,gpu-freq = <200000000>;
- qcom,bus-freq = <1>;
+ qcom,gpu-freq = <550000000>;
+ qcom,bus-freq = <3>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
+ qcom,gpu-freq = <475000000>;
+ qcom,bus-freq = <3>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <3>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <310000000>;
+ qcom,bus-freq = <2>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <200000000>;
+ qcom,bus-freq = <1>;
+ };
+
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <100000000>;
+ qcom,bus-freq = <1>;
+ };
+
+ qcom,gpu-pwrlevel@8 {
+ reg = <8>;
qcom,gpu-freq = <19200000>;
qcom,bus-freq = <0>;
};
diff --git a/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi b/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
index 5ef1add..453531d 100644
--- a/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
@@ -30,7 +30,14 @@
113830 //1094400 kHz
128540 //1152000 kHz
142800 //1209600 kHz
- 157750>; //1363200 kHz
+ 145520 //1248000 kHz
+ 157750 //1363200 kHz
+ 160470 //1401600 kHz
+ 167270 //1497600 kHz
+ 174070 //1593600 kHz
+ 180870 //1689600 kHz
+ 187670 //1785600 kHz
+ 194570>; //1881600 kHz
};
CPU1: cpu@1 {
current = < 23670 //200000 kHz
@@ -41,7 +48,14 @@
113830 //1094400 kHz
128540 //1152000 kHz
142800 //1209600 kHz
- 157750>; //1363200 kHz
+ 145520 //1248000 kHz
+ 157750 //1363200 kHz
+ 160470 //1401600 kHz
+ 167270 //1497600 kHz
+ 174070 //1593600 kHz
+ 180870 //1689600 kHz
+ 187670 //1785600 kHz
+ 194570>; //1881600 kHz
};
CPU2: cpu@2 {
current = < 23670 //200000 kHz
@@ -52,7 +66,14 @@
113830 //1094400 kHz
128540 //1152000 kHz
142800 //1209600 kHz
- 157750>; //1363200 kHz
+ 145520 //1248000 kHz
+ 157750 //1363200 kHz
+ 160470 //1401600 kHz
+ 167270 //1497600 kHz
+ 174070 //1593600 kHz
+ 180870 //1689600 kHz
+ 187670 //1785600 kHz
+ 194570>; //1881600 kHz
};
CPU3: cpu@3 {
current = < 23670 //200000 kHz
@@ -63,7 +84,14 @@
113830 //1094400 kHz
128540 //1152000 kHz
142800 //1209600 kHz
- 157750>; //1363200 kHz
+ 145520 //1248000 kHz
+ 157750 //1363200 kHz
+ 160470 //1401600 kHz
+ 167270 //1497600 kHz
+ 174070 //1593600 kHz
+ 180870 //1689600 kHz
+ 187670 //1785600 kHz
+ 194570>; //1881600 kHz
};
};
diff --git a/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
index c456002..79de247 100644
--- a/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
@@ -17,8 +17,8 @@
compatible = "qcom,spm-regulator";
regulator-name = "8916_s2";
reg = <0x1700 0x100>;
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1350000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1385000>;
};
};
};
@@ -48,10 +48,10 @@
regulator-name = "apc_corner";
qcom,cpr-fuse-corners = <3>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <9>;
+ regulator-max-microvolt = <16>;
- qcom,cpr-voltage-ceiling = <1050000 1150000 1350000>;
- qcom,cpr-voltage-floor = <1050000 1050000 1162500>;
+ qcom,cpr-voltage-ceiling = <1000000 1150000 1385000>;
+ qcom,cpr-voltage-floor = <1000000 1050000 1275000>;
vdd-apc-supply = <&pm8916_s2>;
qcom,vdd-mx-corner-map = <4 5 7>;
@@ -83,9 +83,9 @@
<27 36 6 0>,
<27 18 6 0>,
<27 0 6 0>;
- qcom,cpr-init-voltage-ref = <1050000 1150000 1350000>;
+ qcom,cpr-init-voltage-ref = <1000000 1150000 1385000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3>;
+ qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3 3 3 3 3 3 3 3>;
qcom,cpr-corner-frequency-map =
<1 200000000>,
<2 400000000>,
@@ -95,13 +95,20 @@
<6 1094400000>,
<7 1152000000>,
<8 1209600000>,
- <9 1363200000>;
+ <9 1248000000>,
+ <10 1363200000>,
+ <11 1401600000>,
+ <12 1497600000>,
+ <13 1593600000>,
+ <14 1689600000>,
+ <15 1785600000>,
+ <16 1881600000>;
qcom,speed-bin-fuse-sel = <1 34 3 0>;
qcom,pvs-version-fuse-sel = <0 55 2 0>;
qcom,cpr-speed-bin-max-corners =
- <0 0 2 4 8>,
+ <0 0 2 4 16>,
<0 1 2 4 7>,
- <2 0 2 4 9>;
+ <2 0 2 4 16>;
qcom,cpr-quot-adjust-scaling-factor-max = <650>;
qcom,cpr-enable;
};
diff --git a/arch/arm/boot/dts/qcom/msm8916.dtsi b/arch/arm/boot/dts/qcom/msm8916.dtsi
index 07c754a..b572220 100644
--- a/arch/arm/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916.dtsi
@@ -24,7 +24,7 @@
interrupt-parent = <&intc>;
chosen {
- bootargs = "sched_enable_hmp=1";
+ bootargs = "boot_cpus=0,1,2,3 sched_enable_hmp=1";
};
aliases {
@@ -318,7 +318,15 @@
< 998400000 5>,
< 1094400000 6>,
< 1152000000 7>,
- < 1209600000 8>;
+ < 1209600000 8>,
+ < 1248000000 9>,
+ < 1363200000 10>,
+ < 1401600000 11>,
+ < 1497600000 12>,
+ < 1593600000 13>,
+ < 1689600000 14>,
+ < 1785600000 15>,
+ < 1881600000 16>;
qcom,speed1-bin-v0 =
< 0 0>,
@@ -339,7 +347,15 @@
< 998400000 5>,
< 1094400000 6>,
< 1152000000 7>,
- < 1209600000 8>;
+ < 1209600000 8>,
+ < 1248000000 9>,
+ < 1363200000 10>,
+ < 1401600000 11>,
+ < 1497600000 12>,
+ < 1593600000 13>,
+ < 1689600000 14>,
+ < 1785600000 15>,
+ < 1881600000 16>;
qcom,speed2-bin-v1 =
< 0 0>,
@@ -351,7 +367,14 @@
< 1094400000 6>,
< 1152000000 7>,
< 1209600000 8>,
- < 1363200000 9>;
+ < 1248000000 9>,
+ < 1363200000 10>,
+ < 1401600000 11>,
+ < 1497600000 12>,
+ < 1593600000 13>,
+ < 1689600000 14>,
+ < 1785600000 15>,
+ < 1881600000 16>;
};
cpubw: qcom,cpubw {
@@ -396,7 +419,14 @@
< 1094400 >,
< 1152000 >,
< 1209600 >,
- < 1363200 >;
+ < 1248000 >,
+ < 1363200 >,
+ < 1401600 >,
+ < 1497600 >,
+ < 1593600 >,
+ < 1689600 >,
+ < 1785600 >,
+ < 1881600 >;
};
qcom,sps {
diff --git a/drivers/clk/qcom/clock-gcc-8916.c b/drivers/clk/qcom/clock-gcc-8916.c
index 7ed59c1..c7e4fe94 100644
--- a/drivers/clk/qcom/clock-gcc-8916.c
+++ b/drivers/clk/qcom/clock-gcc-8916.c
@@ -348,6 +348,11 @@ static struct pll_freq_tbl apcs_pll_freq[] = {
F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL(1363200000, 71, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1593600000, 83, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1689600000, 88, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1785600000, 93, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1881600000, 98, 0x0, 0x1, 0x0, 0x0, 0x0),
PLL_F_END
};
@@ -551,7 +556,10 @@ static struct clk_freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
F( 266670000, gpll0, 3, 0, 0),
F( 320000000, gpll0, 2.5, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
- F( 465000000, gpll2, 2, 0, 0),
+ F( 475000000, gpll2, 2, 0, 0),
+ F( 550000000, gpll2, 2, 0, 0),
+ F( 650000000, gpll2, 2, 0, 0),
+ F( 720000000, gpll2, 2, 0, 0),
F_END
};
@@ -565,12 +573,12 @@ static struct rcg_clk vfe0_clk_src = {
.dbg_name = "vfe0_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 160000000, NOMINAL, 320000000, HIGH,
- 465000000),
+ 720000000),
CLK_INIT(vfe0_clk_src.c),
},
};
-static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_465_clk[] = {
+static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_720_clk[] = {
F( 19200000, xo, 1, 0, 0),
F( 50000000, gpll0_aux, 16, 0, 0),
F( 80000000, gpll0_aux, 10, 0, 0),
@@ -582,7 +590,10 @@ static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_465_clk[] = {
F( 294912000, gpll1, 3, 0, 0),
F( 310000000, gpll2, 3, 0, 0),
F( 400000000, gpll0_aux, 2, 0, 0),
- F( 465000000, gpll2, 2, 0, 0),
+ F( 475000000, gpll2, 2, 0, 0),
+ F( 550000000, gpll2, 2, 0, 0),
+ F( 650000000, gpll2, 2, 0, 0),
+ F( 720000000, gpll2, 2, 0, 0),
F_END
};
@@ -598,6 +609,10 @@ static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
F( 294912000, gpll1, 3, 0, 0),
F( 310000000, gpll2, 3, 0, 0),
F( 400000000, gpll0_aux, 2, 0, 0),
+ F( 475000000, gpll2, 2, 0, 0),
+ F( 550000000, gpll2, 2, 0, 0),
+ F( 650000000, gpll2, 2, 0, 0),
+ F( 720000000, gpll2, 2, 0, 0),
F_END
};
@@ -610,8 +625,8 @@ static struct rcg_clk gfx3d_clk_src = {
.c = {
.dbg_name = "gfx3d_clk_src",
.ops = &clk_ops_rcg,
- VDD_DIG_FMAX_MAP3(LOW, 200000000, NOMINAL, 310000000, HIGH,
- 400000000),
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 310000000, HIGH,
+ 720000000),
CLK_INIT(gfx3d_clk_src.c),
},
};
@@ -995,7 +1010,7 @@ static struct rcg_clk csi1phytimer_clk_src = {
static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
F( 160000000, gpll0, 5, 0, 0),
F( 320000000, gpll0, 2.5, 0, 0),
- F( 465000000, gpll2, 2, 0, 0),
+ F( 720000000, gpll2, 2, 0, 0),
F_END
};
@@ -1009,7 +1024,7 @@ static struct rcg_clk cpp_clk_src = {
.dbg_name = "cpp_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 160000000, NOMINAL, 320000000, HIGH,
- 465000000),
+ 720000000),
CLK_INIT(cpp_clk_src.c),
},
};
@@ -2798,8 +2813,8 @@ static void gcc_gfx3d_fmax(struct platform_device *pdev)
pr_info("%s, Version: %d, bin: %d\n", __func__, version,
bin);
- gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 465000000;
- gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_465_clk;
+ gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 720000000;
+ gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_720_clk;
}
static int msm_gcc_probe(struct platform_device *pdev)
--
2.9.3

1369
Patches/LineageOS-15.1/android_kernel_oppo_msm8974/0001-OverUnderClock-EXTREME.patch Normal file
View File

File diff suppressed because it is too large Load Diff

18
Scripts/LineageOS-15.1/Defaults.sh
View File

@ -25,10 +25,10 @@ sed -i '0,/wifi,cell,battery/s/wifi,cell,battery,dnd,flashlight,rotation,bt,airp
#sed -i 's|config_doubleTapOnHomeBehavior">0|config_doubleTapOnHomeBehavior">8|' core/res/res/values/config.xml; #Set double tap home to switch to last app
enter "packages/apps/Dialer"
sed -i 's/FLP_DEFAULT = FLP_GOOGLE;/FLP_DEFAULT = FLP_OPENSTREETMAP;/' src/com/android/dialer/lookup/LookupSettings.java; #Change FLP to OpenStreetMap
sed -i 's/CMSettings.System.ENABLE_FORWARD_LOOKUP, 1)/CMSettings.System.ENABLE_FORWARD_LOOKUP, 0)/' src/com/android/dialer/lookup/LookupSettings.java; #Disable FLP
sed -i 's/CMSettings.System.ENABLE_PEOPLE_LOOKUP, 1)/CMSettings.System.ENABLE_PEOPLE_LOOKUP, 0)/' src/com/android/dialer/lookup/LookupSettings.java; #Disable PLP
sed -i 's/CMSettings.System.ENABLE_REVERSE_LOOKUP, 1)/CMSettings.System.ENABLE_REVERSE_LOOKUP, 0)/' src/com/android/dialer/lookup/LookupSettings.java; #Disable RLP
sed -i 's/FLP_DEFAULT = FLP_GOOGLE;/FLP_DEFAULT = FLP_OPENSTREETMAP;/' java/com/android/dialer/lookup/LookupSettings.java; #Change FLP to OpenStreetMap
sed -i 's/LineageSettings.System.ENABLE_FORWARD_LOOKUP, 1)/CMSettings.System.ENABLE_FORWARD_LOOKUP, 0)/' java/com/android/dialer/lookup/LookupSettings.java; #Disable FLP
sed -i 's/LineageSettings.System.ENABLE_PEOPLE_LOOKUP, 1)/CMSettings.System.ENABLE_PEOPLE_LOOKUP, 0)/' java/com/android/dialer/lookup/LookupSettings.java; #Disable PLP
sed -i 's/LineageSettings.System.ENABLE_REVERSE_LOOKUP, 1)/CMSettings.System.ENABLE_REVERSE_LOOKUP, 0)/' java/com/android/dialer/lookup/LookupSettings.java; #Disable RLP
enter "packages/apps/FDroid"
sed -i 's|DEFAULT_ROOTED = true;|DEFAULT_ROOTED = false;|' app/src/main/java/org/fdroid/fdroid/Preferences.java; #Hide root apps
@ -41,14 +41,8 @@ sed -i 's/static final boolean NFC_ON_DEFAULT = true;/static final boolean NFC_O
sed -i 's/static final boolean NDEF_PUSH_ON_DEFAULT = true;/static final boolean NDEF_PUSH_ON_DEFAULT = false;/' src/com/android/nfc/NfcService.java; #Disable NDEF Push
enter "packages/apps/Settings"
sed -i 's/Settings.Secure.WEB_ACTION_ENABLED, 1/Settings.Secure.WEB_ACTION_ENABLED, 0/' src/com/android/settings/applications/ManageDomainUrls.java; #Disable "Instant Apps"
sed -i 's/Float.parseFloat(newValue.toString()) : 1;/Float.parseFloat(newValue.toString()) : 0.5f;/' src/com/android/settings/DevelopmentSettings.java; #Always reset animation scales to 0.5
enter "packages/apps/Trebuchet"
sed -i 's|homescreen_search_default">true|homescreen_search_default">false|' res/values/preferences_defaults.xml; #Disable search
sed -i 's|drawer_compact_default">false|drawer_compact_default">true|' res/values/preferences_defaults.xml; #Enable compact view
sed -i 's|use_scroller_default">true|use_scroller_default">false|' res/values/preferences_defaults.xml; #Hide scroller
sed -i 's|drawer_search_default">true|drawer_search_default">false|' res/values/preferences_defaults.xml; #Disable search
sed -i 's/Settings.Secure.INSTANT_APPS_ENABLED, 1/Settings.Secure.INSTANT_APPS_ENABLED, 0/' src/com/android/settings/applications/ManageDomainUrls.java; #Disable "Instant Apps"
sed -i 's/Float.parseFloat(newValue.toString()) : 1;/Float.parseFloat(newValue.toString()) : 0.5f;/' src/com/android/settings/development/DevelopmentSettings.java; #Always reset animation scales to 0.5
cd $base
echo "Default settings changed!"

1
Scripts/LineageOS-15.1/Optimize.sh
View File

@ -27,7 +27,6 @@ sed -i 's|config_wifi_fast_bss_transition_enabled">false|config_wifi_fast_bss_tr
sed -i 's|config_wifi_enable_wifi_firmware_debugging">true|config_wifi_enable_wifi_firmware_debugging">false|' core/res/res/values/config.xml;
sed -i 's|config_wifi_supplicant_scan_interval">15000|config_wifi_supplicant_scan_interval">120000|' core/res/res/values/config.xml;
sed -i 's|config_autoBrightnessLightSensorRate">250|config_autoBrightnessLightSensorRate">1000|' core/res/res/values/config.xml;
#sed -i 's|config_buttonLightOnKeypressOnly">false|config_buttonLightOnKeypressOnly">true|' core/res/res/values/config.xml;
sed -i 's|config_recents_use_hardware_layers">false|config_recents_use_hardware_layers">true|' packages/SystemUI/res/values/config.xml;
sed -i 's|config_recents_fake_shadows">false|config_recents_fake_shadows">true|' packages/SystemUI/res/values/config.xml;
sed -i 's|config_notifications_round_rect_clipping">true|config_notifications_round_rect_clipping">false|' packages/SystemUI/res/values/config.xml;

16
Scripts/LineageOS-15.1/Overclock.sh
View File

@ -40,19 +40,19 @@ patch -p1 < $patches"android_kernel_lge_g3/0004-Overclock.patch"
enter "kernel/lge/hammerhead"
patch -p1 < $patches"android_kernel_lge_hammerhead/0001-Overclock.patch" #2.26Ghz -> 2.95Ghz =+2.76Ghz XXX: Untested!
enter "kernel/lge/msm8992"
patch -p1 < $patches"android_kernel_common_msm8992/0001-Overclock.patch"
patch -p1 < $patches"android_kernel_common_msm8992/0003-Overclock.patch"
patch -p1 < $patches"android_kernel_common_msm8992/0004-Overclock.patch"
patch -p1 < $patches"android_kernel_common_msm8992/0005-Overclock.patch"
patch -p1 < $patches"android_kernel_common_msm8992/0006-Overclock.patch"
patch -p1 < $patches"android_kernel_common_msm8992/0007-Overclock.patch"
#enter "kernel/lge/msm8992"
#patch -p1 < $patches"android_kernel_common_msm8992/0001-Overclock.patch"
#patch -p1 < $patches"android_kernel_common_msm8992/0003-Overclock.patch"
#patch -p1 < $patches"android_kernel_common_msm8992/0004-Overclock.patch"
#patch -p1 < $patches"android_kernel_common_msm8992/0005-Overclock.patch"
#patch -p1 < $patches"android_kernel_common_msm8992/0006-Overclock.patch"
#patch -p1 < $patches"android_kernel_common_msm8992/0007-Overclock.patch"
#enter "kernel/motorola/msm8916"
#patch -p1 < $patches"android_kernel_motorola_msm8916/0001-Overclock.patch" #1.36Ghz -> 1.88Ghz =+ 2.07Ghz
enter "kernel/oppo/msm8974"
patch -p1 < $patches"android_kernel_oneplus_msm8974/0001-OverUnderClock-EXTREME.patch" #300Mhz -> 268Mhz, 2.45Ghz -> 2.95Ghz =+2.02Ghz XXX: Not 100% stable under intense workloads
patch -p1 < $patches"android_kernel_oppo_msm8974/0001-OverUnderClock-EXTREME.patch" #300Mhz -> 268Mhz, 2.45Ghz -> 2.95Ghz =+2.02Ghz XXX: Not 100% stable under intense workloads
cd $base
echo "Overclocks applied!"

20
Scripts/LineageOS-15.1/Rebrand.sh
View File

@ -22,24 +22,24 @@ echo "Rebranding..."
enter "bootable/recovery"
sed -i 's|Android Recovery|DivestOS Recovery|' *_ui.cpp;
enter "build"
enter "build/make"
sed -i 's|echo "ro.build.user=$USER"|echo "ro.build.user=emy"|' tools/buildinfo.sh; #Override build user
sed -i 's|echo "ro.build.host=`hostname`"|echo "ro.build.host=dosbm"|' tools/buildinfo.sh; #Override build host
enter "packages/apps/Settings"
sed -i '/.*cmlicense_title/s/LineageOS/DivestOS/' res/values*/cm_strings.xml
sed -i '/.*cmupdate_settings_title/s/LineageOS/DivestOS/' res/values*/cm_strings.xml
sed -i '/.*mod_version/s/LineageOS/DivestOS/' res/values*/cm_strings.xml
#enter "packages/apps/Settings" #TODO: Rebase
#sed -i '/.*cmlicense_title/s/LineageOS/DivestOS/' res/values*/cm_strings.xml
#sed -i '/.*cmupdate_settings_title/s/LineageOS/DivestOS/' res/values*/cm_strings.xml
#sed -i '/.*mod_version/s/LineageOS/DivestOS/' res/values*/cm_strings.xml
enter "packages/apps/SetupWizard"
sed -i 's|http://lineageos.org/legal|https://divestos.xyz/pages/legal/pp.html|' src/com/cyanogenmod/setupwizard/LineageSettingsActivity.java;
sed -i '/.*setup_services/s/LineageOS/DivestOS/' res/values*/strings.xml
sed -i '/.*services_explanation/s/LineageOS/DivestOS/' res/values*/strings.xml
#enter "packages/apps/SetupWizard"
#sed -i 's|http://lineageos.org/legal|https://divestos.xyz/pages/legal/pp.html|' src/com/cyanogenmod/setupwizard/LineageSettingsActivity.java;
#sed -i '/.*setup_services/s/LineageOS/DivestOS/' res/values*/strings.xml
#sed -i '/.*services_explanation/s/LineageOS/DivestOS/' res/values*/strings.xml
enter "packages/apps/Updater"
sed -i 's|>LineageOS|>DivestOS|' res/values*/strings.xml
enter "vendor/cm"
enter "vendor/lineage"
sed -i 's|https://lineageos.org/legal|https://divestos.xyz/pages/about.html|' config/common.mk;
#sed -i '/.*ZIPFILE=/s/lineage/divestos/' build/envsetup.sh
rm -rf bootanimation #TODO: Create a boot animation

9
Scripts/LineageOS-15.1/Theme.sh
View File

@ -46,19 +46,10 @@ enter "packages/apps/GmsCore"
sed -i "s/#ff7fcac3/#ff$themeOverride300/" microg-ui-tools/src/main/res/values/colors.xml
sed -i "s/#ff009688/#ff$themeOverride500/" microg-ui-tools/src/main/res/values/colors.xml
enter "packages/apps/LineageParts"
sed -i "s/#ff009688/#ff$themeOverride500/" res/values/colors.xml
enter "packages/apps/Settings"
sed -i "s/#ff009688/#ff$themeOverride500/" res/values/styles.xml
#TODO: Fix: Storage, Profiles
enter "packages/apps/Trebuchet"
sed -i "s/009688/$themeOverride500/" res/values/*colors.xml
sed -i "s/009688/$themeOverride500/" WallpaperPicker/res/values/colors.xml
mogrify -format png -fill "#$themeOverride500" -opaque "#009688" -fuzz 10% res/drawable*/cling_bg.9.png
#TODO: Fix: Open app icon
enter "packages/apps/Updater"
sed -i "s/#ff009688/#ff$themeOverride500/" res/values/colors.xml