2017-01-27 12:06:04 -05:00
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From 0f5855241796b323b7a71b0c2f02df15b69fbbe1 Mon Sep 17 00:00:00 2001
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2017-01-27 11:54:48 -05:00
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From: nguyenquangduc2000 <nguyenquangduc2000@gmail.com>
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Date: Thu, 7 Jul 2016 15:08:14 +0700
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Subject: [PATCH] Overclock 1.9Ghz/720Mhz
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---
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2017-01-27 12:06:04 -05:00
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arch/arm/boot/dts/qcom/msm8916-gpu.dtsi | 114 ++++++++++++++++++------
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2017-01-27 11:54:48 -05:00
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arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi | 36 +++++++-
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2017-01-27 12:06:04 -05:00
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arch/arm/boot/dts/qcom/msm8916-regulator.dtsi | 27 +++---
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arch/arm/boot/dts/qcom/msm8916.dtsi | 40 +++++++--
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drivers/clk/qcom/clock-gcc-8916.c | 35 +++++---
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5 files changed, 195 insertions(+), 57 deletions(-)
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2017-01-27 11:54:48 -05:00
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diff --git a/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi b/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
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2017-01-27 12:06:04 -05:00
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index 84e183f..d9269d7 100644
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2017-01-27 11:54:48 -05:00
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--- a/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
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+++ b/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
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@@ -27,9 +27,8 @@
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qcom,chipid = <0x03000600>;
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- qcom,initial-pwrlevel = <1>;
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-
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- /* Idle Timeout */
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+ qcom,initial-pwrlevel = <8>;
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+ /* Idle Timeout = msec */
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qcom,idle-timeout = <80>;
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qcom,strtstp-sleepwake;
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@@ -82,30 +81,59 @@
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#size-cells = <0>;
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compatible = "qcom,gpu-pwrlevels";
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+ qcom,gpu-pwrlevel@0 {
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+ reg = <0>;
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+ qcom,gpu-freq = <720000000>;
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+ qcom,bus-freq = <3>;
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+ };
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- qcom,gpu-pwrlevel@0 {
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- reg = <0>;
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- qcom,gpu-freq = <400000000>;
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- qcom,bus-freq = <3>;
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- };
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+ qcom,gpu-pwrlevel@1 {
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+ reg = <1>;
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+ qcom,gpu-freq = <650000000>;
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+ qcom,bus-freq = <3>;
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+ };
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- qcom,gpu-pwrlevel@1 {
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- reg = <1>;
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- qcom,gpu-freq = <310000000>;
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- qcom,bus-freq = <2>;
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- };
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+ qcom,gpu-pwrlevel@2 {
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+ reg = <2>;
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+ qcom,gpu-freq = <550000000>;
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+ qcom,bus-freq = <3>;
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+ };
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- qcom,gpu-pwrlevel@2 {
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- reg = <2>;
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- qcom,gpu-freq = <200000000>;
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- qcom,bus-freq = <1>;
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- };
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+ qcom,gpu-pwrlevel@3 {
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+ reg = <3>;
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+ qcom,gpu-freq = <475000000>;
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+ qcom,bus-freq = <3>;
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+ };
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- qcom,gpu-pwrlevel@3 {
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- reg = <3>;
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- qcom,gpu-freq = <19200000>;
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- qcom,bus-freq = <0>;
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- };
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+ qcom,gpu-pwrlevel@4 {
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+ reg = <4>;
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+ qcom,gpu-freq = <400000000>;
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+ qcom,bus-freq = <3>;
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+ };
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+
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+ qcom,gpu-pwrlevel@5 {
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+ reg = <5>;
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+ qcom,gpu-freq = <310000000>;
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+ qcom,bus-freq = <2>;
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+ };
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+
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+ qcom,gpu-pwrlevel@6 {
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+ reg = <6>;
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+ qcom,gpu-freq = <200000000>;
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+ qcom,bus-freq = <1>;
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+ };
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+
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+ qcom,gpu-pwrlevel@7 {
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+ reg = <7>;
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+ qcom,gpu-freq = <100000000>;
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+ qcom,bus-freq = <1>;
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+ };
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+
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+ qcom,gpu-pwrlevel@8 {
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+ reg = <8>;
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+ qcom,gpu-freq = <19200000>;
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+ qcom,bus-freq = <0>;
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+ };
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};
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/* Speed levels */
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qcom,gpu-speed-config@2 {
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@@ -129,24 +157,54 @@
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qcom,gpu-pwrlevel@0 {
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reg = <0>;
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- qcom,gpu-freq = <465000000>;
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+ qcom,gpu-freq = <720000000>;
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qcom,bus-freq = <3>;
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};
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qcom,gpu-pwrlevel@1 {
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reg = <1>;
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- qcom,gpu-freq = <310000000>;
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- qcom,bus-freq = <2>;
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+ qcom,gpu-freq = <650000000>;
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+ qcom,bus-freq = <3>;
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};
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qcom,gpu-pwrlevel@2 {
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reg = <2>;
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- qcom,gpu-freq = <200000000>;
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- qcom,bus-freq = <1>;
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+ qcom,gpu-freq = <550000000>;
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+ qcom,bus-freq = <3>;
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};
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qcom,gpu-pwrlevel@3 {
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reg = <3>;
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+ qcom,gpu-freq = <475000000>;
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+ qcom,bus-freq = <3>;
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+ };
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+
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+ qcom,gpu-pwrlevel@4 {
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+ reg = <4>;
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+ qcom,gpu-freq = <400000000>;
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+ qcom,bus-freq = <3>;
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+ };
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+
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+ qcom,gpu-pwrlevel@5 {
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+ reg = <5>;
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+ qcom,gpu-freq = <310000000>;
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+ qcom,bus-freq = <2>;
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+ };
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+
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+ qcom,gpu-pwrlevel@6 {
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+ reg = <6>;
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+ qcom,gpu-freq = <200000000>;
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+ qcom,bus-freq = <1>;
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+ };
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+
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+ qcom,gpu-pwrlevel@7 {
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+ reg = <7>;
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+ qcom,gpu-freq = <100000000>;
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+ qcom,bus-freq = <1>;
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+ };
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+
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+ qcom,gpu-pwrlevel@8 {
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+ reg = <8>;
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qcom,gpu-freq = <19200000>;
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qcom,bus-freq = <0>;
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};
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diff --git a/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi b/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
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2017-01-27 12:06:04 -05:00
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index 5ef1add..453531d 100644
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2017-01-27 11:54:48 -05:00
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--- a/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
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+++ b/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
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@@ -30,7 +30,14 @@
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113830 //1094400 kHz
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128540 //1152000 kHz
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142800 //1209600 kHz
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- 157750>; //1363200 kHz
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+ 145520 //1248000 kHz
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+ 157750 //1363200 kHz
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+ 160470 //1401600 kHz
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+ 167270 //1497600 kHz
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+ 174070 //1593600 kHz
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+ 180870 //1689600 kHz
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+ 187670 //1785600 kHz
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+ 194570>; //1881600 kHz
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};
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CPU1: cpu@1 {
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current = < 23670 //200000 kHz
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@@ -41,7 +48,14 @@
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113830 //1094400 kHz
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128540 //1152000 kHz
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142800 //1209600 kHz
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- 157750>; //1363200 kHz
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+ 145520 //1248000 kHz
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+ 157750 //1363200 kHz
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+ 160470 //1401600 kHz
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+ 167270 //1497600 kHz
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+ 174070 //1593600 kHz
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+ 180870 //1689600 kHz
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+ 187670 //1785600 kHz
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+ 194570>; //1881600 kHz
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};
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CPU2: cpu@2 {
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current = < 23670 //200000 kHz
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@@ -52,7 +66,14 @@
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113830 //1094400 kHz
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128540 //1152000 kHz
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142800 //1209600 kHz
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- 157750>; //1363200 kHz
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+ 145520 //1248000 kHz
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+ 157750 //1363200 kHz
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+ 160470 //1401600 kHz
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+ 167270 //1497600 kHz
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+ 174070 //1593600 kHz
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+ 180870 //1689600 kHz
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+ 187670 //1785600 kHz
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+ 194570>; //1881600 kHz
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};
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CPU3: cpu@3 {
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current = < 23670 //200000 kHz
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@@ -63,7 +84,14 @@
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113830 //1094400 kHz
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128540 //1152000 kHz
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142800 //1209600 kHz
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- 157750>; //1363200 kHz
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+ 145520 //1248000 kHz
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+ 157750 //1363200 kHz
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+ 160470 //1401600 kHz
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+ 167270 //1497600 kHz
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+ 174070 //1593600 kHz
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+ 180870 //1689600 kHz
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+ 187670 //1785600 kHz
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+ 194570>; //1881600 kHz
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};
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};
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diff --git a/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
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index c456002..79de247 100644
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--- a/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
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+++ b/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
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@@ -17,8 +17,8 @@
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compatible = "qcom,spm-regulator";
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regulator-name = "8916_s2";
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reg = <0x1700 0x100>;
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- regulator-min-microvolt = <1050000>;
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- regulator-max-microvolt = <1350000>;
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1385000>;
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};
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};
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};
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@@ -48,10 +48,10 @@
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regulator-name = "apc_corner";
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qcom,cpr-fuse-corners = <3>;
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regulator-min-microvolt = <1>;
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- regulator-max-microvolt = <9>;
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+ regulator-max-microvolt = <16>;
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- qcom,cpr-voltage-ceiling = <1050000 1150000 1350000>;
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- qcom,cpr-voltage-floor = <1050000 1050000 1162500>;
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+ qcom,cpr-voltage-ceiling = <1000000 1150000 1385000>;
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+ qcom,cpr-voltage-floor = <1000000 1050000 1275000>;
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vdd-apc-supply = <&pm8916_s2>;
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qcom,vdd-mx-corner-map = <4 5 7>;
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@@ -83,9 +83,9 @@
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<27 36 6 0>,
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<27 18 6 0>,
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<27 0 6 0>;
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- qcom,cpr-init-voltage-ref = <1050000 1150000 1350000>;
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+ qcom,cpr-init-voltage-ref = <1000000 1150000 1385000>;
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qcom,cpr-init-voltage-step = <10000>;
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- qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3>;
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+ qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3 3 3 3 3 3 3 3>;
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qcom,cpr-corner-frequency-map =
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<1 200000000>,
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<2 400000000>,
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@@ -95,13 +95,20 @@
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<6 1094400000>,
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<7 1152000000>,
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<8 1209600000>,
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- <9 1363200000>;
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+ <9 1248000000>,
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+ <10 1363200000>,
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+ <11 1401600000>,
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+ <12 1497600000>,
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+ <13 1593600000>,
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+ <14 1689600000>,
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+ <15 1785600000>,
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+ <16 1881600000>;
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qcom,speed-bin-fuse-sel = <1 34 3 0>;
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qcom,pvs-version-fuse-sel = <0 55 2 0>;
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qcom,cpr-speed-bin-max-corners =
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- <0 0 2 4 8>,
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+ <0 0 2 4 16>,
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<0 1 2 4 7>,
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- <2 0 2 4 9>;
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+ <2 0 2 4 16>;
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qcom,cpr-quot-adjust-scaling-factor-max = <650>;
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qcom,cpr-enable;
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};
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diff --git a/arch/arm/boot/dts/qcom/msm8916.dtsi b/arch/arm/boot/dts/qcom/msm8916.dtsi
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2017-01-27 12:06:04 -05:00
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index 07c754a..b572220 100644
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2017-01-27 11:54:48 -05:00
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--- a/arch/arm/boot/dts/qcom/msm8916.dtsi
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+++ b/arch/arm/boot/dts/qcom/msm8916.dtsi
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@@ -24,7 +24,7 @@
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interrupt-parent = <&intc>;
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chosen {
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- bootargs = "sched_enable_hmp=1";
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+ bootargs = "boot_cpus=0,1,2,3 sched_enable_hmp=1";
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};
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aliases {
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@@ -318,7 +318,15 @@
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< 998400000 5>,
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< 1094400000 6>,
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< 1152000000 7>,
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- < 1209600000 8>;
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+ < 1209600000 8>,
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+ < 1248000000 9>,
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+ < 1363200000 10>,
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+ < 1401600000 11>,
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+ < 1497600000 12>,
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+ < 1593600000 13>,
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+ < 1689600000 14>,
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+ < 1785600000 15>,
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+ < 1881600000 16>;
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qcom,speed1-bin-v0 =
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< 0 0>,
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@@ -339,7 +347,15 @@
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< 998400000 5>,
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< 1094400000 6>,
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< 1152000000 7>,
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- < 1209600000 8>;
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+ < 1209600000 8>,
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+ < 1248000000 9>,
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+ < 1363200000 10>,
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+ < 1401600000 11>,
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+ < 1497600000 12>,
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+ < 1593600000 13>,
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+ < 1689600000 14>,
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+ < 1785600000 15>,
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+ < 1881600000 16>;
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qcom,speed2-bin-v1 =
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< 0 0>,
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@@ -351,7 +367,14 @@
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< 1094400000 6>,
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< 1152000000 7>,
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< 1209600000 8>,
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- < 1363200000 9>;
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+ < 1248000000 9>,
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+ < 1363200000 10>,
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+ < 1401600000 11>,
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+ < 1497600000 12>,
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+ < 1593600000 13>,
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+ < 1689600000 14>,
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+ < 1785600000 15>,
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+ < 1881600000 16>;
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};
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cpubw: qcom,cpubw {
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@@ -396,7 +419,14 @@
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< 1094400 >,
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< 1152000 >,
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< 1209600 >,
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- < 1363200 >;
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+ < 1248000 >,
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+ < 1363200 >,
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+ < 1401600 >,
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+ < 1497600 >,
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+ < 1593600 >,
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+ < 1689600 >,
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+ < 1785600 >,
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+ < 1881600 >;
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};
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qcom,sps {
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diff --git a/drivers/clk/qcom/clock-gcc-8916.c b/drivers/clk/qcom/clock-gcc-8916.c
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2017-01-27 12:06:04 -05:00
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index 7ed59c1..c7e4fe94 100644
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2017-01-27 11:54:48 -05:00
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--- a/drivers/clk/qcom/clock-gcc-8916.c
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+++ b/drivers/clk/qcom/clock-gcc-8916.c
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2017-01-27 12:06:04 -05:00
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@@ -348,6 +348,11 @@ static struct pll_freq_tbl apcs_pll_freq[] = {
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2017-01-27 11:54:48 -05:00
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F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
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F_APCS_PLL(1363200000, 71, 0x0, 0x1, 0x0, 0x0, 0x0),
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F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
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+ F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
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+ F_APCS_PLL(1593600000, 83, 0x0, 0x1, 0x0, 0x0, 0x0),
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+ F_APCS_PLL(1689600000, 88, 0x0, 0x1, 0x0, 0x0, 0x0),
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+ F_APCS_PLL(1785600000, 93, 0x0, 0x1, 0x0, 0x0, 0x0),
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+ F_APCS_PLL(1881600000, 98, 0x0, 0x1, 0x0, 0x0, 0x0),
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PLL_F_END
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};
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2017-01-27 12:06:04 -05:00
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@@ -551,7 +556,10 @@ static struct clk_freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
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2017-01-27 11:54:48 -05:00
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F( 266670000, gpll0, 3, 0, 0),
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F( 320000000, gpll0, 2.5, 0, 0),
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F( 400000000, gpll0, 2, 0, 0),
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- F( 465000000, gpll2, 2, 0, 0),
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+ F( 475000000, gpll2, 2, 0, 0),
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+ F( 550000000, gpll2, 2, 0, 0),
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+ F( 650000000, gpll2, 2, 0, 0),
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+ F( 720000000, gpll2, 2, 0, 0),
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F_END
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};
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2017-01-27 12:06:04 -05:00
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@@ -565,12 +573,12 @@ static struct rcg_clk vfe0_clk_src = {
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2017-01-27 11:54:48 -05:00
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.dbg_name = "vfe0_clk_src",
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.ops = &clk_ops_rcg,
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VDD_DIG_FMAX_MAP3(LOW, 160000000, NOMINAL, 320000000, HIGH,
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- 465000000),
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+ 720000000),
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CLK_INIT(vfe0_clk_src.c),
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},
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};
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-static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_465_clk[] = {
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+static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_720_clk[] = {
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F( 19200000, xo, 1, 0, 0),
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F( 50000000, gpll0_aux, 16, 0, 0),
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F( 80000000, gpll0_aux, 10, 0, 0),
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2017-01-27 12:06:04 -05:00
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@@ -582,7 +590,10 @@ static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_465_clk[] = {
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2017-01-27 11:54:48 -05:00
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F( 294912000, gpll1, 3, 0, 0),
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F( 310000000, gpll2, 3, 0, 0),
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F( 400000000, gpll0_aux, 2, 0, 0),
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- F( 465000000, gpll2, 2, 0, 0),
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+ F( 475000000, gpll2, 2, 0, 0),
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+ F( 550000000, gpll2, 2, 0, 0),
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+ F( 650000000, gpll2, 2, 0, 0),
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+ F( 720000000, gpll2, 2, 0, 0),
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F_END
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};
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2017-01-27 12:06:04 -05:00
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@@ -598,6 +609,10 @@ static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
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2017-01-27 11:54:48 -05:00
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F( 294912000, gpll1, 3, 0, 0),
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F( 310000000, gpll2, 3, 0, 0),
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F( 400000000, gpll0_aux, 2, 0, 0),
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+ F( 475000000, gpll2, 2, 0, 0),
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+ F( 550000000, gpll2, 2, 0, 0),
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+ F( 650000000, gpll2, 2, 0, 0),
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+ F( 720000000, gpll2, 2, 0, 0),
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F_END
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};
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2017-01-27 12:06:04 -05:00
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@@ -610,8 +625,8 @@ static struct rcg_clk gfx3d_clk_src = {
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2017-01-27 11:54:48 -05:00
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.c = {
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.dbg_name = "gfx3d_clk_src",
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.ops = &clk_ops_rcg,
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- VDD_DIG_FMAX_MAP3(LOW, 200000000, NOMINAL, 310000000, HIGH,
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- 400000000),
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+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 310000000, HIGH,
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+ 720000000),
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CLK_INIT(gfx3d_clk_src.c),
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},
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};
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2017-01-27 12:06:04 -05:00
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@@ -995,7 +1010,7 @@ static struct rcg_clk csi1phytimer_clk_src = {
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2017-01-27 11:54:48 -05:00
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static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
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F( 160000000, gpll0, 5, 0, 0),
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F( 320000000, gpll0, 2.5, 0, 0),
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- F( 465000000, gpll2, 2, 0, 0),
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+ F( 720000000, gpll2, 2, 0, 0),
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F_END
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};
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2017-01-27 12:06:04 -05:00
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@@ -1009,7 +1024,7 @@ static struct rcg_clk cpp_clk_src = {
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2017-01-27 11:54:48 -05:00
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.dbg_name = "cpp_clk_src",
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.ops = &clk_ops_rcg,
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VDD_DIG_FMAX_MAP3(LOW, 160000000, NOMINAL, 320000000, HIGH,
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- 465000000),
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+ 720000000),
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CLK_INIT(cpp_clk_src.c),
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},
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};
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2017-01-27 12:06:04 -05:00
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@@ -2798,8 +2813,8 @@ static void gcc_gfx3d_fmax(struct platform_device *pdev)
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2017-01-27 11:54:48 -05:00
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pr_info("%s, Version: %d, bin: %d\n", __func__, version,
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bin);
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- gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 465000000;
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- gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_465_clk;
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+ gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 720000000;
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+ gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_720_clk;
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}
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static int msm_gcc_probe(struct platform_device *pdev)
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2017-01-27 12:06:04 -05:00
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--
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2.9.3
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