mirror of
https://github.com/Divested-Mobile/DivestOS-Build.git
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110 lines
4.0 KiB
Diff
110 lines
4.0 KiB
Diff
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From 8d6d2378e62e1b5236eea4f35d4405e0271cf4d5 Mon Sep 17 00:00:00 2001
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From: anarkia1976 <stefano.villa1976@gmail.com>
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Date: Wed, 30 Apr 2014 15:04:21 +0200
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Subject: [PATCH] msm: cpu: overclock: modded for cpu ultra overclock and
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normal
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---
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arch/arm/mach-msm/Kconfig | 7 ++++++-
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arch/arm/mach-msm/acpuclock-8064.c | 16 ++++++++++++----
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2 files changed, 18 insertions(+), 5 deletions(-)
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diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
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index 814ab1a88b4..b79e485f71f 100644
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--- a/arch/arm/mach-msm/Kconfig
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+++ b/arch/arm/mach-msm/Kconfig
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@@ -1643,8 +1643,13 @@ config CPU_OVERCLOCK
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bool "Enable CPU Overclocking option"
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default n
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help
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- Krait overclocking up to 1.9 GHz
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+ Krait overclocking up to 1.7 GHz
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+config CPU_OVERCLOCK_ULTRA
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+ bool "Enable CPU Overclocking option"
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+ default n
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+ help
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+ Krait overclocking up to 1.9 GHz
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config MSM_AVS_HW
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bool "Enable Adaptive Voltage Scaling (AVS)"
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diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
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index 611776ed185..03974d36bba 100644
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--- a/arch/arm/mach-msm/acpuclock-8064.c
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+++ b/arch/arm/mach-msm/acpuclock-8064.c
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@@ -47,7 +47,7 @@ static struct scalable scalable[] __initdata = {
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x4501,
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-#ifdef CONFIG_CPU_OVERCLOCK
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+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
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.vreg[VREG_CORE] = { "krait0", 1450000 },
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#else
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.vreg[VREG_CORE] = { "krait0", 1300000 },
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@@ -62,7 +62,7 @@ static struct scalable scalable[] __initdata = {
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x5501,
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-#ifdef CONFIG_CPU_OVERCLOCK
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+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
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.vreg[VREG_CORE] = { "krait1", 1450000 },
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#else
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.vreg[VREG_CORE] = { "krait1", 1300000 },
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@@ -77,7 +77,7 @@ static struct scalable scalable[] __initdata = {
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x6501,
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-#ifdef CONFIG_CPU_OVERCLOCK
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+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
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.vreg[VREG_CORE] = { "krait2", 1450000 },
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#else
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.vreg[VREG_CORE] = { "krait2", 1300000 },
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@@ -92,7 +92,7 @@ static struct scalable scalable[] __initdata = {
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x7501,
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-#ifdef CONFIG_CPU_OVERCLOCK
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+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
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.vreg[VREG_CORE] = { "krait3", 1450000 },
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#else
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.vreg[VREG_CORE] = { "krait3", 1300000 },
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@@ -210,6 +210,8 @@ static struct acpu_level tbl_slow[] __initdata = {
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#ifdef CONFIG_CPU_OVERCLOCK
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{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 },
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+#endif
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+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
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{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1400000 },
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{ 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1425000 },
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{ 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1450000 },
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@@ -250,6 +252,8 @@ static struct acpu_level tbl_nom[] __initdata = {
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#ifdef CONFIG_CPU_OVERCLOCK
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{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 },
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+#endif
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+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
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{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1350000 },
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{ 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1375000 },
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{ 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1400000 },
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@@ -290,6 +294,8 @@ static struct acpu_level tbl_fast[] __initdata = {
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#ifdef CONFIG_CPU_OVERCLOCK
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{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
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+#endif
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+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
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{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1300000 },
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{ 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1325000 },
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{ 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1350000 },
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@@ -330,6 +336,8 @@ static struct acpu_level tbl_faster[] __initdata = {
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#ifdef CONFIG_CPU_OVERCLOCK
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{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1150000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 },
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+#endif
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+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
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{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 },
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{ 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1275000 },
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{ 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1300000 },
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--
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2.15.1
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