DivestOS/Patches/Overclocks/android_kernel_lge_mako/0004-Overclock.patch

From 8d6d2378e62e1b5236eea4f35d4405e0271cf4d5 Mon Sep 17 00:00:00 2001
From: anarkia1976 <stefano.villa1976@gmail.com>
Date: Wed, 30 Apr 2014 15:04:21 +0200
Subject: [PATCH] msm: cpu: overclock: modded for cpu ultra overclock and
 normal

---
 arch/arm/mach-msm/Kconfig          |  7 ++++++-
 arch/arm/mach-msm/acpuclock-8064.c | 16 ++++++++++++----
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 814ab1a88b4..b79e485f71f 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1643,8 +1643,13 @@ config CPU_OVERCLOCK
 	bool "Enable CPU Overclocking option"
 	default n
 	help
-	  Krait overclocking up to 1.9 GHz
+	  Krait overclocking up to 1.7 GHz
 
+config CPU_OVERCLOCK_ULTRA
+        bool "Enable CPU Overclocking option"
+        default n
+        help
+          Krait overclocking up to 1.9 GHz
 
 config MSM_AVS_HW
 	bool "Enable Adaptive Voltage Scaling (AVS)"
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 611776ed185..03974d36bba 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -47,7 +47,7 @@ static struct scalable scalable[] __initdata = {
 		.aux_clk_sel = 3,
 		.sec_clk_sel = 2,
 		.l2cpmr_iaddr = 0x4501,
-#ifdef CONFIG_CPU_OVERCLOCK
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
 		.vreg[VREG_CORE] = { "krait0", 1450000 },
 #else
 		.vreg[VREG_CORE] = { "krait0", 1300000 },
@@ -62,7 +62,7 @@ static struct scalable scalable[] __initdata = {
 		.aux_clk_sel = 3,
 		.sec_clk_sel = 2,
 		.l2cpmr_iaddr = 0x5501,
-#ifdef CONFIG_CPU_OVERCLOCK
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
 		.vreg[VREG_CORE] = { "krait1", 1450000 },
 #else
 		.vreg[VREG_CORE] = { "krait1", 1300000 },
@@ -77,7 +77,7 @@ static struct scalable scalable[] __initdata = {
 		.aux_clk_sel = 3,
 		.sec_clk_sel = 2,
 		.l2cpmr_iaddr = 0x6501,
-#ifdef CONFIG_CPU_OVERCLOCK
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
 		.vreg[VREG_CORE] = { "krait2", 1450000 },
 #else
 		.vreg[VREG_CORE] = { "krait2", 1300000 },
@@ -92,7 +92,7 @@ static struct scalable scalable[] __initdata = {
 		.aux_clk_sel = 3,
 		.sec_clk_sel = 2,
 		.l2cpmr_iaddr = 0x7501,
-#ifdef CONFIG_CPU_OVERCLOCK
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
 		.vreg[VREG_CORE] = { "krait3", 1450000 },
 #else
 		.vreg[VREG_CORE] = { "krait3", 1300000 },
@@ -210,6 +210,8 @@ static struct acpu_level tbl_slow[] __initdata = {
 #ifdef CONFIG_CPU_OVERCLOCK
 	{ 1, {  1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 },
 	{ 1, {  1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 },
+#endif
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
 	{ 1, {  1836000, HFPLL, 1, 0x44 }, L2(15), 1400000 },
 	{ 1, {  1890000, HFPLL, 1, 0x45 }, L2(15), 1425000 },
 	{ 1, {  1944000, HFPLL, 1, 0x46 }, L2(15), 1450000 },
@@ -250,6 +252,8 @@ static struct acpu_level tbl_nom[] __initdata = {
 #ifdef CONFIG_CPU_OVERCLOCK
 	{ 1, {  1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
 	{ 1, {  1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 },
+#endif
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
 	{ 1, {  1836000, HFPLL, 1, 0x44 }, L2(15), 1350000 },
 	{ 1, {  1890000, HFPLL, 1, 0x45 }, L2(15), 1375000 },
 	{ 1, {  1944000, HFPLL, 1, 0x46 }, L2(15), 1400000 },
@@ -290,6 +294,8 @@ static struct acpu_level tbl_fast[] __initdata = {
 #ifdef CONFIG_CPU_OVERCLOCK
 	{ 1, {  1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 },
 	{ 1, {  1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
+#endif
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
 	{ 1, {  1836000, HFPLL, 1, 0x44 }, L2(15), 1300000 },
 	{ 1, {  1890000, HFPLL, 1, 0x45 }, L2(15), 1325000 },
 	{ 1, {  1944000, HFPLL, 1, 0x46 }, L2(15), 1350000 },
@@ -330,6 +336,8 @@ static struct acpu_level tbl_faster[] __initdata = {
 #ifdef CONFIG_CPU_OVERCLOCK
 	{ 1, {  1620000, HFPLL, 1, 0x3C }, L2(15), 1150000 },
 	{ 1, {  1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 },
+#endif
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
 	{ 1, {  1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 },
 	{ 1, {  1890000, HFPLL, 1, 0x45 }, L2(15), 1275000 },
 	{ 1, {  1944000, HFPLL, 1, 0x46 }, L2(15), 1300000 },
-- 
2.15.1