mirror of
https://github.com/Divested-Mobile/DivestOS-Build.git
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337 lines
15 KiB
Diff
337 lines
15 KiB
Diff
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From b557b85341913b39dc667a48ea52451bb5b0a75e Mon Sep 17 00:00:00 2001
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From: faux123 <reioux@gmail.com>
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Date: Sun, 29 Jul 2012 00:22:34 -0700
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Subject: [PATCH 1/5] Overclocking: enable CPU overclocking
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this is done via speedo id hax by forcing Nexus 7 Tegra3 to identify as
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AP33 variant instead of as T33
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---
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arch/arm/mach-tegra/Kconfig | 7 +++++++
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arch/arm/mach-tegra/tegra3_speedo.c | 15 +++++++++++++++
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2 files changed, 22 insertions(+)
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diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
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index 37d3f11cdd5..a4159c60eeb 100644
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--- a/arch/arm/mach-tegra/Kconfig
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+++ b/arch/arm/mach-tegra/Kconfig
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@@ -700,6 +700,13 @@ config TEGRA_PLLM_RESTRICTED
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disabled, PLLM is used as a clock source with no restrictions (which
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may effectively increase lower limit for core voltage).
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+config TEGRA_CPU_OVERCLOCK
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+ bool "Tegra3 CPU Overclocking"
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+ depends on ARCH_TEGRA_3x_SOC
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+ default n
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+ help
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+ Tegra3 CPU overclocking
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+
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config TEGRA_WDT_RECOVERY
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bool "Enable suspend/resume watchdog recovery mechanism"
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default n
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diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c
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index d9a3bbbe99e..b7a3142ebe6 100644
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--- a/arch/arm/mach-tegra/tegra3_speedo.c
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+++ b/arch/arm/mach-tegra/tegra3_speedo.c
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@@ -246,9 +246,16 @@ static void rev_sku_to_speedo_ids(int rev, int sku)
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case 0x83: /* T30L or T30S */
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switch (package_id) {
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case 1: /* MID => T30L */
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+#ifdef CONFIG_TEGRA_CPU_OVERCLOCK
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+ /* fake it to behave as AP33 variant */
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+ cpu_speedo_id = 4;
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+ soc_speedo_id = 1;
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+ threshold_index = 7;
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+#else
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cpu_speedo_id = 7;
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soc_speedo_id = 1;
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threshold_index = 10;
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+#endif
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break;
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case 2: /* DSC => T30S */
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cpu_speedo_id = 3;
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@@ -445,7 +452,11 @@ void tegra_init_speedo_data(void)
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break;
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}
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}
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+#if CONFIG_TEGRA_CPU_OVERCLOCK
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+ cpu_process_id = 3; /* fake it to behave as AP33 cpu variant 3 */
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+#else
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cpu_process_id = iv -1;
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+#endif
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if (cpu_process_id == -1) {
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pr_err("****************************************************");
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@@ -465,7 +476,11 @@ void tegra_init_speedo_data(void)
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break;
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}
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}
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+#if CONFIG_TEGRA_CPU_OVERCLOCK
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+ core_process_id = 1; /* fake it to behave as AP33 core variant 1 */
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+#else
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core_process_id = iv -1;
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+#endif
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if (core_process_id == -1) {
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pr_err("****************************************************");
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--
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2.18.0
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From 39e22197dc10a0d53dbfe646b33976f93d572492 Mon Sep 17 00:00:00 2001
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From: faux123 <reioux@gmail.com>
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Date: Fri, 3 Aug 2012 21:50:57 -0700
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Subject: [PATCH 2/5] Overclocking: GPU overclocking from 416MHz to 520Mhz
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---
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arch/arm/mach-tegra/Kconfig | 7 +++++++
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arch/arm/mach-tegra/tegra3_dvfs.c | 14 ++++++++++++++
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2 files changed, 21 insertions(+)
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diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
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index a4159c60eeb..92cab1a6049 100644
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--- a/arch/arm/mach-tegra/Kconfig
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+++ b/arch/arm/mach-tegra/Kconfig
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@@ -707,6 +707,13 @@ config TEGRA_CPU_OVERCLOCK
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help
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Tegra3 CPU overclocking
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+config TEGRA_GPU_OVERCLOCK
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+ bool "Tegra3 GPU Overclocking"
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+ depends on ARCH_TEGRA_3x_SOC
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+ default n
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+ help
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+ Tegra3 GPU overclocking
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+
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config TEGRA_WDT_RECOVERY
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bool "Enable suspend/resume watchdog recovery mechanism"
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default n
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diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
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index 2f2f09edf57..84c47aa11af 100644
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--- a/arch/arm/mach-tegra/tegra3_dvfs.c
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+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
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@@ -290,6 +290,15 @@ static struct dvfs core_dvfs_table[] = {
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CORE_DVFS("vi", 2, 1, KHZ, 1, 219000, 267000, 300000, 371000, 409000, 425000, 425000, 425000),
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CORE_DVFS("vi", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 470000, 470000, 470000),
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+#ifdef CONFIG_TEGRA_GPU_OVERCLOCK
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+ CORE_DVFS("vde", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
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+ CORE_DVFS("mpe", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
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+ CORE_DVFS("2d", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
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+ CORE_DVFS("epp", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
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+ CORE_DVFS("3d", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
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+ CORE_DVFS("3d2", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
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+ CORE_DVFS("se", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
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+#else
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CORE_DVFS("vde", 0, 1, KHZ, 1, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
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CORE_DVFS("mpe", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
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CORE_DVFS("2d", 0, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
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@@ -297,6 +306,7 @@ static struct dvfs core_dvfs_table[] = {
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CORE_DVFS("3d", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
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CORE_DVFS("3d2", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
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CORE_DVFS("se", 0, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
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+#endif
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CORE_DVFS("vde", 1, 1, KHZ, 200000, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
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CORE_DVFS("mpe", 1, 1, KHZ, 200000, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
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@@ -327,7 +337,11 @@ static struct dvfs core_dvfs_table[] = {
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CORE_DVFS("host1x", 2, 1, KHZ, 100000, 152000, 188000, 222000, 254000, 267000, 267000, 267000, 300000),
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CORE_DVFS("host1x", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 242000, 242000, 242000),
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+#ifdef CONFIG_TEGRA_GPU_OVERCLOCK
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+ CORE_DVFS("cbus", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
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+#else
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CORE_DVFS("cbus", 0, 1, KHZ, 1, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
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+#endif
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CORE_DVFS("cbus", 1, 1, KHZ, 200000, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
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CORE_DVFS("cbus", 2, 1, KHZ, 200000, 247000, 304000, 352000, 400000, 437000, 484000, 520000, 600000),
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CORE_DVFS("cbus", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 484000, 484000, 484000),
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--
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2.18.0
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From 014b0edd51cb109bb83e9fe6729c039bf641919c Mon Sep 17 00:00:00 2001
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From: faux123 <reioux@gmail.com>
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Date: Sat, 4 Aug 2012 14:30:44 -0700
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Subject: [PATCH 3/5] Overclock: add ultimate edition to allow quadcore up to
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1.55 GHz
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Also add Tegra3 Gaming Fix to disallow 1 single core to have higher
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frequecy than rest
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---
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arch/arm/mach-tegra/Kconfig | 14 ++++++++++++++
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arch/arm/mach-tegra/edp.c | 11 +++++++++++
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arch/arm/mach-tegra/tegra3_dvfs.c | 5 ++++-
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3 files changed, 29 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
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index 92cab1a6049..b82662df89c 100644
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--- a/arch/arm/mach-tegra/Kconfig
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+++ b/arch/arm/mach-tegra/Kconfig
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@@ -707,6 +707,13 @@ config TEGRA_CPU_OVERCLOCK
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help
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Tegra3 CPU overclocking
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+config TEGRA_CPU_OVERCLOCK_ULTIMATE
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+ bool "Tegra3 CPU Overclocking Ultimate"
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+ depends on ARCH_TEGRA_3x_SOC && TEGRA_CPU_OVERCLOCK
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+ default n
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+ help
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+ Tegra3 CPU overclocking Ultimate edition
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+
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config TEGRA_GPU_OVERCLOCK
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bool "Tegra3 GPU Overclocking"
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depends on ARCH_TEGRA_3x_SOC
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@@ -714,6 +721,13 @@ config TEGRA_GPU_OVERCLOCK
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help
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Tegra3 GPU overclocking
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+config TEGRA_GAMING_FIX
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+ bool "Tegra3 Gaming Fix"
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+ depends on ARCH_TEGRA_3x_SOC
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+ default n
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+ help
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+ Tegra3 Quadcore Gaming Fix
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+
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config TEGRA_WDT_RECOVERY
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bool "Enable suspend/resume watchdog recovery mechanism"
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default n
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diff --git a/arch/arm/mach-tegra/edp.c b/arch/arm/mach-tegra/edp.c
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index 713853637a5..8a5e3566088 100644
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--- a/arch/arm/mach-tegra/edp.c
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+++ b/arch/arm/mach-tegra/edp.c
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@@ -778,10 +778,21 @@ static int __init init_cpu_edp_limits_lookup(void)
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for (j = 0; j < edp_limits_size; j++) {
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e[j].temperature = (int)t[i+j].temperature;
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+#ifdef CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE
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+ e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]+5) * 10000;
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+ e[j].freq_limits[1] = (unsigned int)(t[i+j].freq_limits[1]+15) * 10000;
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+ e[j].freq_limits[2] = (unsigned int)(t[i+j].freq_limits[2]+15) * 10000;
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+ e[j].freq_limits[3] = (unsigned int)(t[i+j].freq_limits[3]+15) * 10000;
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+#else
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+#ifdef CONFIG_TEGRA_GAMING_FIX
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+ e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]-10) * 10000;
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+#else
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e[j].freq_limits[0] = (unsigned int)t[i+j].freq_limits[0]*10000;
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+#endif
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e[j].freq_limits[1] = (unsigned int)t[i+j].freq_limits[1]*10000;
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e[j].freq_limits[2] = (unsigned int)t[i+j].freq_limits[2]*10000;
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e[j].freq_limits[3] = (unsigned int)t[i+j].freq_limits[3]*10000;
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+#endif
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}
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if (edp_limits != edp_default_limits)
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diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
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index 84c47aa11af..23b472742c2 100644
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--- a/arch/arm/mach-tegra/tegra3_dvfs.c
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+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
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@@ -199,8 +199,11 @@ static struct dvfs cpu_dvfs_table[] = {
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CPU_DVFS("cpu_g", 4, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1240, 1240, 1280, 1280, 1320, 1320, 1360, 1360, 1500),
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CPU_DVFS("cpu_g", 4, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1360, 1360, 1400, 1400, 1500),
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CPU_DVFS("cpu_g", 4, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1340, 1340, 1380, 1380, 1500),
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+#ifdef CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE
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+ CPU_DVFS("cpu_g", 4, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1550, 1550, 1600),
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+#else
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CPU_DVFS("cpu_g", 4, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1500),
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-
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+#endif
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CPU_DVFS("cpu_g", 5, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700),
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CPU_DVFS("cpu_g", 5, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700),
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--
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2.18.0
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From bd6e9cb668affd03706557566ec1694941ec16d4 Mon Sep 17 00:00:00 2001
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From: faux123 <reioux@gmail.com>
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Date: Wed, 29 Aug 2012 23:11:22 -0700
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Subject: [PATCH 4/5] overclock: boost ultimate from 1.55 quad to 1.6 quad
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also boost the dot pixel clock from 68MHz to 85MHz
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---
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arch/arm/mach-tegra/board-grouper-panel.c | 4 ++++
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arch/arm/mach-tegra/edp.c | 8 ++++----
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arch/arm/mach-tegra/tegra3_dvfs.c | 2 +-
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3 files changed, 9 insertions(+), 5 deletions(-)
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diff --git a/arch/arm/mach-tegra/board-grouper-panel.c b/arch/arm/mach-tegra/board-grouper-panel.c
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index 44e00674dfc..a2ffaf7ab24 100644
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--- a/arch/arm/mach-tegra/board-grouper-panel.c
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+++ b/arch/arm/mach-tegra/board-grouper-panel.c
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@@ -219,7 +219,11 @@ static struct resource grouper_disp1_resources[] = {
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static struct tegra_dc_mode grouper_panel_modes[] = {
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{
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/* 1280x800@60Hz */
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+#ifdef CONFIG_TEGRA_GPU_OVERCLOCK
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.pclk = 68000000,
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+#else
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+ .pclk = 85000000,
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+#endif
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.h_ref_to_sync = 1,
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.v_ref_to_sync = 1,
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.h_sync_width = 24,
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diff --git a/arch/arm/mach-tegra/edp.c b/arch/arm/mach-tegra/edp.c
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index 8a5e3566088..bd37f9de86e 100644
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--- a/arch/arm/mach-tegra/edp.c
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+++ b/arch/arm/mach-tegra/edp.c
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@@ -779,10 +779,10 @@ static int __init init_cpu_edp_limits_lookup(void)
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for (j = 0; j < edp_limits_size; j++) {
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e[j].temperature = (int)t[i+j].temperature;
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#ifdef CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE
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- e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]+5) * 10000;
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- e[j].freq_limits[1] = (unsigned int)(t[i+j].freq_limits[1]+15) * 10000;
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- e[j].freq_limits[2] = (unsigned int)(t[i+j].freq_limits[2]+15) * 10000;
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- e[j].freq_limits[3] = (unsigned int)(t[i+j].freq_limits[3]+15) * 10000;
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+ e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]+10) * 10000;
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+ e[j].freq_limits[1] = (unsigned int)(t[i+j].freq_limits[1]+20) * 10000;
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+ e[j].freq_limits[2] = (unsigned int)(t[i+j].freq_limits[2]+20) * 10000;
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+ e[j].freq_limits[3] = (unsigned int)(t[i+j].freq_limits[3]+20) * 10000;
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#else
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#ifdef CONFIG_TEGRA_GAMING_FIX
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e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]-10) * 10000;
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diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
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index 23b472742c2..9af43c1adb7 100644
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--- a/arch/arm/mach-tegra/tegra3_dvfs.c
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+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
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@@ -200,7 +200,7 @@ static struct dvfs cpu_dvfs_table[] = {
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CPU_DVFS("cpu_g", 4, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1360, 1360, 1400, 1400, 1500),
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CPU_DVFS("cpu_g", 4, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1340, 1340, 1380, 1380, 1500),
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#ifdef CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE
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- CPU_DVFS("cpu_g", 4, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1550, 1550, 1600),
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+ CPU_DVFS("cpu_g", 4, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1550, 1600, 1700),
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#else
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CPU_DVFS("cpu_g", 4, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1500),
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#endif
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--
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2.18.0
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From 54fa5d91acc795e7818d522bacf1767bfc7a3b8c Mon Sep 17 00:00:00 2001
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From: faux123 <reioux@gmail.com>
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Date: Tue, 4 Sep 2012 19:22:55 -0700
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Subject: [PATCH 5/5] board/panel: remove pclk boost (causing screen tearing)
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|
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---
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arch/arm/mach-tegra/board-grouper-panel.c | 4 ----
|
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1 file changed, 4 deletions(-)
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diff --git a/arch/arm/mach-tegra/board-grouper-panel.c b/arch/arm/mach-tegra/board-grouper-panel.c
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index a2ffaf7ab24..44e00674dfc 100644
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--- a/arch/arm/mach-tegra/board-grouper-panel.c
|
||
|
|
+++ b/arch/arm/mach-tegra/board-grouper-panel.c
|
||
|
|
@@ -219,11 +219,7 @@ static struct resource grouper_disp1_resources[] = {
|
||
|
|
static struct tegra_dc_mode grouper_panel_modes[] = {
|
||
|
|
{
|
||
|
|
/* 1280x800@60Hz */
|
||
|
|
-#ifdef CONFIG_TEGRA_GPU_OVERCLOCK
|
||
|
|
.pclk = 68000000,
|
||
|
|
-#else
|
||
|
|
- .pclk = 85000000,
|
||
|
|
-#endif
|
||
|
|
.h_ref_to_sync = 1,
|
||
|
|
.v_ref_to_sync = 1,
|
||
|
|
.h_sync_width = 24,
|
||
|
|
--
|
||
|
|
2.18.0
|
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